Unified tessellation circuit and method therefor

Abstract

A hardware tessellation circuit serves as a unified hardware parametric coordinate generator for providing parametric coordinates for tessellation. The tessellation circuit includes control logic that receives tessellation instruction information, such as an instruction indicating which type of multiple tessellation operations to perform, on an incoming primitive wherein the different types of tessellation include discrete tessellation, continuous tessellation and adaptive tessellation. The tessellation circuit also includes shared tessellation logic that is controlled by the control logic, and includes a plurality of shared logic units, such as arithmetic logic units, that are controllable by the control logic based on the type of tessellation detected to be used for the incoming primitive. The shared tessellation logic is controlled to reuse at least some of the logic units for two different tessellation operations defined by the tessellation type information.

1 . A tessellation circuit comprising:
 (a) control logic operative to determine which one of a plurality of different types of tessellation processes are to be performed on an input primitive; and   (b) shared hardware tessellation logic, controlled by the control logic, and including a plurality of shared hardware logic units that are reusable for different types of tessellation processes, wherein the shared tessellation hardware logic is operative to reuse at least one of the shared hardware logic units for at least two different types of tessellation processes.   
   
   
       2 . The tessellation circuit of  claim 1  wherein the different tessellation process types include at least two of the following: discrete tessellation, continuous tessellation, and adaptive tessellation. 
   
   
       3 . The tessellation circuit of  claim 1  wherein the shared hardware logic units include at least setup logic, walker logic, and output logic, each comprising logic units that are controllable by the control logic. 
   
   
       4 . The tessellation circuit of  claim 3  wherein the setup logic includes interpolators that are reused for both adaptive and continuous tessellation types and wherein the tessellation circuit produces parametric coordinates for use in determining subprimitive vertices. 
   
   
       5 . The tessellation circuit of  claim 3  wherein the shared hardware tessellation logic is controlled by the control logic to generate parametric coordinate data for all of the different types of primitives from the group of lines, triangles, quad primitives, line patches, tri patches, and rectangular patches. 
   
   
       6 . The tessellation circuit of  claim 3  wherein the shared hardware tessellation logic produces at least one of: barycentric coordinate data, reordered vertex indice data, and quad primitive identification data depending upon a type of incoming primitive. 
   
   
       7 . The tessellation circuit of  claim 3  wherein the walker logic is comprised of a state machine and wherein states of the state machine are shared for continuous and adaptive tessellation operations. 
   
   
       8 . A method for tessellating primitives comprising: controlling shared hardware tessellation logic to reuse at least one of a plurality of shared hardware logic units for at least two different tessellation process types. 
   
   
       9 . The method of  claim 8  comprising determining which one of a plurality of different types of tessellation processes to be performed on the input primitive; and wherein the different types of tessellation include at least one of the following: discrete tessellation, continuous tessellation, and adaptive tessellation. 
   
   
       10 . The method of  claim 8  wherein the method includes reusing interpolators for both adaptive and continuous tessellation types and wherein the tessellation circuit produces parametric coordinates for use in determining subprimitive vertices. 
   
   
       11 . The method of  claim 8  wherein the method includes generating coordinate data for all of the different types of primitives from the group of lines, triangles, quad primitives, line patches, tri patches, and rectangular patches. 
   
   
       12 . The method of  claim 8  wherein the method includes producing at least one of: barycentric coordinate data, recorded vertex indice data, and quad primitive identification data depending upon a type of incoming primitive. 
   
   
       13 . The tessellation circuit of  claim 8  wherein one of the shared logic units is an edge walker comprised of a state machine, wherein states of the state machine are shared for continuous and adaptive tessellation operations. 
   
   
       14 . A method for tessellating primitives comprising:
 (a) determining which one of a plurality of different types of tessellation processes to be performed on the input primitive wherein the different types of tessellation include at least one of the following: discrete tessellation, continuous tessellation, and adaptive tessellation; and   (b) controlling shared hardware tessellation logic to reuse interpolators for both adaptive and continuous tessellation types and wherein the method comprises producing parametric coordinates for use in determining subprimitive vertices using the reused interpolators.