Synchronous semiconductor device, and inspection system and method for the same

Abstract

The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carry out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will resent a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.

1 . A method of inspecting a synchronous semiconductor device alternately transiting them between an activated state and an inactivated state in order to carry out a test in the activated state, comprising the steps of:
 detecting an inactivating signal a predetermined period of time before the activated state;   transiting to the inactivated state;   then latching a synchronization activating signal in synchronism with first synchronization timing in a synchronization signal; and   transiting to the activated state.   
     
     
         2 . A method of inspecting a synchronous semiconductor device alternately transiting between an activated state and an inactivated state in order to carry out a test in the activated state, comprising the steps of:
 latching a synchronization inactivating signal in synchronism with first synchronization timing in a synchronization signal;   transiting to the inactivated state;   detecting an activating signal a predetermined period of time after the inactivated state; and   transiting to the active state.