Semiconductor structures formed on substrates and methods of manufacturing the same

Abstract

A semiconductor apparatus includes a metal substrate, a doped silicon layer on the metal substrate, a semiconductor layer overlying the doped silicon layer, and semiconductor structures having one or more p-n junctions at least partially within the semiconductor layer formed by using layering, patterning, and doping steps. In an embodiment, the doped silicon layer comprises a heavily doped silicon layer. In another embodiment, the doped silicon region has a thickness that is less than a thickness of a cleavable region formed by ion implantation. In a specific embodiment, the thickness of the cleavable region is about 1-2 um. In another embodiment, the semiconductor layer has a thickness of approximately 10 um. In another embodiment, the semiconductor structures includes a vertical power MOSFET with the metal substrate configured to be a drain terminal contact region.

1 . A semiconductor apparatus, comprising:
 a metal substrate;   a doped silicon layer on the metal substrate;   a semiconductor layer overlying the doped silicon layer; and   semiconductor structures having one or more p-n junctions at least partially within the semiconductor layer formed by using layering, patterning, and doping steps.   
   
   
       2 . The apparatus of  claim 1 , wherein the doped silicon layer comprises a heavily doped silicon layer. 
   
   
       3 . The apparatus of  claim 1 , wherein the doped silicon region has a thickness that is less than a thickness of a cleavable region formed by ion implantation. 
   
   
       4 . The apparatus of  claim 3 , wherein the thickness of the cleavable region is about 1-2 um. 
   
   
       5 . The apparatus of  claim 1 , wherein the semiconductor layer has a thickness of approximately 10 um. 
   
   
       6 . The apparatus of  claim 1 , wherein the semiconductor layer overlying the doped silicon layer comprises an epitaxial layer on the doped silicon layer. 
   
   
       7 . The apparatus of  claim 1 , wherein the metal substrate is configured to electrically contact the doped silicon layer and provide structural support to the semiconductor apparatus. 
   
   
       8 . The apparatus of  claim 1 , wherein the semiconductor structures comprise a vertical power MOSFET with the metal substrate configured to be a drain terminal contact region. 
   
   
       9 . The apparatus of  claim 1 , wherein the semiconductor structures comprise a vertical power MOSFET with the doped silicon region configured to be a drain region. 
   
   
       10 . A semiconductor apparatus on a metal substrate, comprising:
 a doped silicon layer having a thickness that is less than a thickness of a cleavable region formed by ion implantation;   a semiconductor layer overlying the doped silicon layer;   semiconductor structures having one or more p-n junctions at least partially within the semiconductor layer formed by using layering, patterning, and doping steps; and   a sufficient amount of metal in contact with the doped silicon layer to form a metal substrate.   
   
   
       11 . The apparatus of  claim 10 , wherein the doped silicon layer comprises a heavily doped silicon layer. 
   
   
       12 . The apparatus of  claim 10 , wherein the thickness of the cleavable region is about 1-2 um. 
   
   
       13 . The apparatus of  claim 10 , wherein the doped silicon layer has a thickness of less than about 1-2 um. 
   
   
       14 . The apparatus of  claim 10 , wherein the semiconductor layer overlying the doped silicon layer comprises an epitaxial layer on the doped silicon layer. 
   
   
       15 . The apparatus of  claim 10 , wherein the semiconductor layer has a thickness of approximately 10 um. 
   
   
       16 . The method of  claim 10 , wherein the metal substrate is configured to electrically contact the doped silicon layer and provide structural support to the semiconductor apparatus. 
   
   
       17 . The method of  claim 10 , wherein the semiconductor structures comprise a vertical power MOSFET with the metal substrate configured to be a drain terminal contact region. 
   
   
       18 . The method of  claim 10 , wherein the semiconductor structures comprise a vertical power MOSFET with the doped silicon region configured to be a drain region.