Serial flash semiconductor memory

Abstract

A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.

1 . A method for executing code from a flash memory, comprising:
 obtaining a multiple bit segment of an instruction from the flash memory;   processing the multiple bit instruction segment in a controller to initiate decode of the instruction;   obtaining an additional multiple bit segment of the instruction from the flash memory;   processing the additional multiple bit instruction segment in the controller to continue decode of the instruction;   repeating the additional multiple bit instruction segment obtaining step and the additional multiple bit instruction segment processing step until the instruction is fully decoded; and   executing the decoded instruction.   
   
   
       2 . A method for executing code from a flash memory, comprising:
 obtaining a multiple bit segment of an instruction from the flash memory;   storing the multiple bit instruction segment in a controller;   obtaining an additional multiple bit segment of the instruction from the flash memory;   storing the additional multiple bit instruction segment in the controller;   repeating the additional multiple bit instruction segment obtaining step and the additional multiple bit instruction segment storing step until the instruction is fully assembled; and   decoding the instruction promptly upon full assembly thereof.