Plastic Semiconductor Package Having Improved Control of Dimensions

Abstract

A device with a semiconductor chip assembled on a planar substrate and encapsulation compound surrounding the assembled chip and a portion of the substrate near the chip; the compound has a planar top area. The encapsulation compound has a plurality of side areas reaching from the substrate to the top area; these side areas form edge lines with the top area, where the top area plane intersects with the respective plane of each side area. The encapsulation compound is recessed along the edge lines so that the material is caved-in along the lines; this feature causes the recess to prevent any compound from the side area planes to reach the top area plane, whereby the planarity of the top area is preserved.

1 . A semiconductor device comprising:
 an insulating substrate having an encapsulation compound structure at a central region bordering a peripheral region at the edges of the substrate;   a first semiconductor chip attached to the central region of the substrate and encapsulated with the encapsulation compound structure;   the encapsulation compound structure having a flat top surface substantially parallel the substrate, and side surfaces inclining from the substrate towards the flat top surface;   a step structure between the flat top surface and the flat side surfaces having a base surface bordering the side surfaces and a shoulder surface extending between the base surface and the top surface;   the base surface having a width between the side surfaces and the shoulder surface, the shoulder surface having a height between the top surface and the base surface; and   the height being less than the width.   
   
   
       2 . The semiconductor device of  claim 1 ; in which the first semiconductor chip is wire bonded to the substrate. 
   
   
       3 . The semiconductor device of  claim 2 , further comprising contact pads in the peripheral region not encapsulated with the encapsulation compound, electrically communicable to the semiconductor chip. 
   
   
       4 . The semiconductor device of  claim 1 ; further comprising a second semiconductor chip affixed on the first semiconductor chip. 
   
   
       5 . The semiconductor device of  claim 1 ; in which the base surface is closer to the top surface than the bond wire is. 
   
   
       6 . The semiconductor device of  claim 4 ; in which the second semiconductor chip is wire bonded to the substrate. 
   
   
       7 . A package on package device having a bottom device comprising:
 an insulating substrate having an encapsulation compound structure at a central region bordering a peripheral region at the edges of the substrate;   a first semiconductor chip attached to the central region of the substrate and encapsulated with the encapsulation compound structure;   the encapsulation compound structure having a flat top surface substantially parallel the substrate, and side surfaces inclining from the substrate towards the flat top surface;   a step structure between the flat top surface and the flat side surfaces having a base surface bordering the side surfaces and a shoulder surface extending between the base surface and the top surface;   the base surface having a width between the side surfaces and the shoulder surface, the shoulder surface having a height between the top surface and the base surface; and   the height being less than the width.   
   
   
       8 . The package on package device of  claim 7 ; in which the first semiconductor chip is wire bonded to the substrate. 
   
   
       9 . The package on package device of  claim 8 , further comprising contact pads in the peripheral region not encapsulated with the encapsulation compound, electrically communicable to the semiconductor chip. 
   
   
       10 . The package on package device of  claim 7 ; further comprising a second semiconductor chip affixed on the first semiconductor chip. 
   
   
       11 . The package on package device of  claim 7 ; in which the base surface is closer to the top surface than the bond wire is. 
   
   
       12 . The package on package device of  claim 11 ; in which the second semiconductor chip is wire bonded to the substrate.