Analysis of stress impact on transistor performance

Abstract

Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

1 . A system for approximating stress-induced effect on a transistor property in a region-of-interest in an integrated circuit layout, the system being configured to:
 approximate the stress independently in at least first and second different dimensions, at each of a plurality of sample points in the region-of-interest;   convert the stress approximations at each of the sample points to a respective transistor property adjustment value; and   combine the transistor property adjustment values at all the sample points in the plurality of sample points.   
   
   
       2 . A system according to  claim 1 ., wherein the transistor property comprises transistor threshold voltage. 
   
   
       3 . A system according to  claim 1 ., wherein the transistor property comprises a doping profile in a transistor channel. 
   
   
       4 . A system according to  claim 1 , wherein the transistor property comprises carrier mobility, and converting the stress approximations at each of the sample points to a respective transistor property adjustment value comprises converting the stress approximations at each of the sample points to a respective mobility enhancement value. 
   
   
       5 . A system according to  claim 4 , wherein converting the stress approximations at each of the sample points to a respective mobility enhancement value comprises, for each subject one of the sample points:
 converting the approximated stress at the subject sample point in each of the dimensions to a respective mobility enhancement value for that dimension at the subject sample point; and   combining the mobility enhancement values for all the dimensions at the subject sample point to develop the mobility enhancement value for the subject sample point.   
   
   
       6 . A system according to  claim 5 , wherein converting the approximated stress at the subject sample point in each of the dimensions to a respective mobility enhancement value for that dimension at the subject sample point comprises:
 evaluating a first conversion function of the approximated stress in a first one of the dimensions at the subject sample point; and   evaluating a second conversion function of the approximated stress in a second one of the dimensions at the subject sample point,   wherein the first and second conversion functions are different.   
   
   
       7 . A system according to  claim 4 , wherein the region-of-interest is the channel region of a transistor. 
   
   
       8 . A system for approximating stress-induced mobility enhancement in a plurality of transistors in the integrated circuit layout, the system being configured to:
 perform the steps of  claim 4  for each of more than 12 transistors in the integrated circuit layout, the region-of-interest for each of the transistors being a channel region of the transistor.   
   
   
       9 . A system according to  claim 4 , wherein approximating the stress at each of a plurality of sample points in the region-of-interest comprises, for a particular one of the dimensions and for each subject one of the sample points, includes:
 approximating the stress contributions in the particular dimension at the subject sample point due to each of a plurality of stress generation mechanisms; and   combining the contributions to the stress in the particular dimension at the subject sample point approximated due to all of the stress generation mechanisms, to develop a combined stress in the particular dimension at the subject sample point.   
   
   
       10 . A system according to  claim 4 , wherein approximating the stress at each of a plurality of sample points in the region-of-interest comprises, for each given one of the dimensions and for each subject one of the sample points, includes:
 for each particular one of a plurality of edges within a search region for the given sample point, approximating a first stress contribution due to the particular edge to the stress in the given dimension at the subject sample point; and   combining the contributions to the stress in the given dimension at the subject sample point approximated due to all the edges in the plurality of edges, to develop a combined stress in the given dimension at the subject sample point.   
   
   
       11 . A system according to  claim 10 , wherein approximating a first stress contribution due to the particular edge to the stress in the given dimension at the subject sample point, comprises:
 approximating the stress contributions due to a particular edge to the stress in the given dimension at the subject sample point due to each of a plurality of stress generation mechanisms; and   combining the stress contributions due to the particular edge to the stress in the given dimension at the subject sample point approximated due to all of the stress generation mechanisms, to develop a combined stress in the given dimension at the subject sample point due to the particular edge,   and wherein converting the stress approximation at each of the sample points to a respective mobility enhancement value comprises, for each subject one of the sample points:   converting the approximated stress at the subject sample point in each of the dimensions to a respective mobility enhancement value for that dimension at the subject sample point; and   combining the mobility enhancement values for all the dimensions at the subject sample point to develop the mobility enhancement value for the subject sample point.   
   
   
       12 . A system for approximating stress-induced variation of a transistor property due to stress in a transistor channel region in an integrated circuit layout, the system being configured to develop the approximation in dependence upon stresses oriented transversely along the width of the channel. 
   
   
       13 . A system according to  claim 12 , wherein the variation of a transistor property comprises mobility enhancement. 
   
   
       14 . A system according to  claim 12 , wherein the variation of a transistor property comprises variation of a transistor threshold voltage. 
   
   
       15 . A system according to  claim 12 , wherein the variation of a transistor property comprises variation of a doping profile in the channel. 
   
   
       16 . A system for approximating stress-induced variation of a transistor property due to stress in a transistor channel region in an integrated circuit layout, the system being configured to develop the approximation in dependence upon stresses oriented in at least two lateral dimensions across the channel. 
   
   
       17 . A system according to  claim 16 , wherein the variation of a transistor property comprises mobility enhancement. 
   
   
       18 . A system according to  claim 16 , wherein the variation of a transistor property comprises variation of a transistor threshold voltage. 
   
   
       19 . A system according to  claim 16 , wherein the variation of a transistor property comprises variation of a doping profile in the channel. 
   
   
       20 . A system for approximating stress-induced variation of a transistor property in a transistor channel region in an integrated circuit layout, the system being configured to develop the approximation in dependence upon stresses caused by layout feature edges that are oriented parallel to the longitudinal dimension of the transistor. 
   
   
       21 . A system according to  claim 20 , wherein the variation of a transistor property comprises mobility enhancement. 
   
   
       22 . A system according to  claim 20 , wherein the variation of a transistor property comprises variation of a transistor threshold voltage. 
   
   
       23 . A system according to  claim 20 , wherein the variation of a transistor property comprises variation of a doping profile in the channel. 
   
   
       24 . A system for approximating stress-induced variation of a transistor property due to stress in a transistor channel region in a first diffusion region in an integrated circuit layout, the system being configured to develop the approximation in dependence upon both a stress contribution arising due to a first materials interface at an edge of the first diffusion region, and a stress contribution arising due to a second materials interface outside the first diffusion region. 
   
   
       25 . A system according to  claim 24 , wherein the variation of a transistor property comprises mobility enhancement. 
   
   
       26 . A system according to  claim 24 , wherein the variation of a transistor property comprises variation of a transistor threshold voltage. 
   
   
       27 . A system according to  claim 24 , wherein the variation of a transistor property comprises variation of a doping profile in the channel. 
   
   
       28 . A system for approximating stress-induced variation of a transistor property due to stress in a transistor channel region in an integrated circuit layout, the system being configured to develop the approximation in dependence upon stresses induced in the channel by each of a plurality of different stress generation mechanisms. 
   
   
       29 . A system according to  claim 28 , wherein the variation of a transistor property comprises mobility enhancement. 
   
   
       30 . A system according to  claim 28 , wherein the variation of a transistor property comprises variation of a transistor threshold voltage. 
   
   
       31 . A system according to  claim 28 , wherein the variation of a transistor property comprises variation of a doping profile in the channel.