Memory device having highly integrated cell structure and method of its fabrication

Abstract

In an embodiment, a memory device, with a highly integrated cell structure, includes a mold insulating layer disposed on a semiconductor substrate. At least one conductive line is disposed on the mold insulating layer. Data storage elements self-aligned with the conductive line are interposed between the conductive line and the mold insulating layer. In this case, each of the data storage elements may include a resistor pattern and a barrier pattern, which are sequentially stacked, and the resistor pattern may be self-aligned with the barrier pattern.

1 . A memory device comprising:
 a mold insulating layer disposed over a semiconductor substrate;   a conductive line having sides disposed over the mold insulating layer; and   a data storage element interposed between the conductive line and the mold insulating layer so that sides of the data storage elements are aligned with the sides of the conductive line.   
   
   
       2 . The memory device according to  claim 1 , wherein the data storage element includes a resistor pattern and a barrier pattern that are sequentially stacked, the resistor pattern being self-aligned with the barrier pattern. 
   
   
       3 . The memory device according to  claim 2 , wherein the resistor pattern includes a phase-change material layer. 
   
   
       4 . The memory device according to  claim 2 , wherein the barrier pattern comprises a metal nitride layer. 
   
   
       5 . The memory device according to  claim 1 , wherein the conductive line includes a metal nitride layer and a metal layer that are sequentially stacked. 
   
   
       6 . The memory device according to  claim 1 , further comprising an insulating material layer pattern that covers opposite sidewalls of the data storage elements, the opposite sidewalls being substantially parallel to a widthwise direction of the conductive line. 
   
   
       7 . The memory device according to  claim 6 , wherein the insulating material layer pattern is arranged in a line to fill regions between the data storage elements, and to cross the conductive line. 
   
   
       8 . The memory device according to  claim 7 , further comprising a protective insulating layer pattern interposed between the insulating material layer pattern and the data storage element and between the insulating material layer pattern and the mold insulating layer. 
   
   
       9 . The memory device according to  claim 1 , further comprising a semiconductor pattern and a lower electrode interposed between the semiconductor substrate and the data storage element wherein the semiconductor pattern and the lower electrode are sequentially stacked on the semiconductor substrate through the mold insulating layer. 
   
   
       10 . The memory device according to  claim 9 , wherein the semiconductor pattern constitutes a vertical-contact-type cell diode. 
   
   
       11 . The memory device according to  claim 9 , further comprising an insulating contact spacer interposed between the mold insulating layer and the lower electrode. 
   
   
       12 . A memory device comprising:
 a mold insulating layer disposed on a semiconductor substrate;   a cell diode hole disposed in the mold insulating layer and including a cell diode;   a lower electrode disposed on the cell diode and in the cell diode hole;   a bit line disposed over the cell diode; and   a data storage element interposed between the bit line and the cell diode, the data storage element self-aligned with the bit line.   
   
   
       13 . The memory device according to  claim 12 , wherein the data storage element includes a resistor pattern and a barrier pattern that are sequentially stacked, the resistor pattern being self-aligned with the barrier pattern. 
   
   
       14 . The memory device according to  claim 13 , wherein the resistor pattern includes a phase-change material layer.