US2010025848A1PendingUtilityA1
Method of fabricating a semiconductor device and semiconductor device
Est. expiryAug 4, 2028(~2 yrs left)· nominal 20-yr term from priority
H10W 74/10H10W 72/9413H10W 72/241H10W 72/29H10W 70/60H10W 90/701H10W 74/117H10W 74/014H10W 72/0198H10W 70/09H10W 70/635
51
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Claims
Abstract
A method of fabricating a semiconductor device and semiconductor device is provided. The method provides a first layer. The first layer includes through-holes. At least one semiconductor chip is provided. The semiconductor chip includes contact elements. The semiconductor chip is placed onto the first layer with the contact elements being aligned with the through-holes. An encapsulant material is applied over the semiconductor chip.
Claims
exact text as granted — not AI-modified1 . A method of fabricating a semiconductor device, comprising:
providing a first layer, the first layer comprising through-holes; providing at least one semiconductor chip, the semiconductor chip defining a first surface comprising contact elements and a second surface opposite to the first surface of the semiconductor chip; placing the semiconductor chip onto the first layer with the first surface facing the first layer; and applying an encapsulant material over the second surface of the semiconductor chip.
2 . The method of claim 1 , further comprising:
placing the semiconductor chip onto the first layer with the contact elements being aligned with the through-holes.
3 . The method of claim 1 , further comprising forming the through-holes by at least one of stamping, laser drilling, and selective etching the first layer.
4 . The method of claim 1 , wherein the first layer is an insulating layer.
5 . The method of claim 1 , wherein the first layer is comprised of a first insulation layer facing the semiconductor chip and a metal layer facing away from the semiconductor chip.
6 . The method of claim 1 , further comprising attaching the first layer to a second layer.
7 . The method of claim 6 , further comprising separating the second layer from the first layer after placing the semiconductor chip onto the first layer.
8 . The method of claim 1 , further comprising fabricating an encapsulated structure having a shape of a wafer.
9 . The method of claim 1 , further comprising fabricating an encapsulated structure having a rectangular shape.
10 . A method of fabricating a semiconductor device, comprising:
providing a first layer, the first layer comprising through-holes; providing at least one semiconductor chip, the semiconductor chip comprising contact elements; placing the semiconductor chip onto the first layer with the contact elements being aligned with the through-holes; and applying an encapsulant material over the semiconductor chip.
11 . The method of claim 10 , further comprising
the semiconductor chip defining a first surface comprising the contact elements and a second surface opposite to the first surface, and placing the semiconductor chip onto the first layer with the first surface facing the first layer.
12 . The method of claim 10 , further comprising forming the through-holes by at least one of stamping, laser drilling, or selective etching the first layer.
13 . The method of claim 10 , wherein the first layer is an insulating layer.
14 . The method of claim 10 , wherein the first layer is comprised of a first insulation layer facing the semiconductor chip and a metal layer facing away from the semiconductor chip.
15 . The method of claim 10 , further comprising attaching the first layer to a second layer.
16 . The method of claim 15 , further comprising separating the second layer from the first layer after placing the semiconductor chip onto the first layer.
17 . The method of claim 10 , further comprising fabricating an encapsulated structure having a shape of a wafer.
18 . The method of claim 10 , further comprising fabricating an encapsulated structure having a rectangular shape.
19 . A method of fabricating a plurality of semiconductor devices, comprising:
providing a first layer, the first layer comprising through-holes; providing a plurality of semiconductor chips, each one of the semiconductor chips defining a first surface comprising contact elements and a second surface opposite to the first surface of the semiconductor chips and side surfaces between the first and second surfaces, respectively; placing the semiconductor chips onto the first layer with the first surface facing the first layer; applying an encapsulant material over at least the side surfaces of the semiconductor chips; applying a conducting layer over the first layer and the contact elements, the conducting layer comprising conducting areas, each one of the conducting areas connected with one of the contact elements, respectively; and dividing the resulting structure into semiconductor devices.
20 . The method of claim 19 , further comprising placing the semiconductor chips onto the first layer with the contact elements being aligned with the through-holes.
21 . The method of claim 19 , further comprising forming the through-holes by at least one of stamping, laser drilling, or selective etching the first layer.
22 . The method of claim 19 , wherein the first layer is an insulating layer.
23 . The method of claim 19 , wherein the first layer is comprised of a first insulation layer facing the semiconductor chips and a metal layer facing away from the semiconductor chips.
24 . The method of claim 19 , further comprising attaching the first layer to a second layer.
25 . The method of claim 24 , further comprising separating the second layer from the first layer after placing the semiconductor chips onto the first layer.
26 . The method of claim 19 , further comprising fabricating an encapsulated structure having a shape of a wafer.
27 . The method of claim 19 , further comprising fabricating an encapsulated structure having a rectangular shape.
28 . A semiconductor device, comprising:
at least one semiconductor chip comprising contact elements on a first surface of the chip; a encapsulant material covering at least partly the semiconductor chip; a dielectric layer situated on the first surface of the chip, a dielectric layer situated on the first surface of the chip, the dielectric layer comprising vias aligned with the contact elements; and a layer of a conductive material covering a surface of the dielectric layer above the vias, the conductive material produced by applying conductive ink to the surface and one or more of drying, curing and sintering the conductive ink.
29 . The semiconductor device of claim 28 , further comprising:
a conducting layer comprising contact areas, each one of the contact areas connected with the vias, respectively.
30 . The semiconductor device of claim 29 , further comprising:
a solder resist layer applied above the conducting layer, the solder resist layer comprising openings above the contact areas.
31 . The semiconductor device of claim 30 , further comprising:
solder balls applied above the openings of the solder resist layer, the solder balls being electrically connected to the contact areas, respectively.
32 . A semiconductor device, comprising:
at least one semiconductor chip comprising contact elements on a first surface of the semiconductor chip; an encapsulant material covering at least partly the semiconductor chip; a dielectric layer situated on the first surface of the semiconductor chip, the dielectric layer comprising vias aligned with the contact elements; and a layer of a conductive material covering a surface of the dielectric layer above the vias, the conductive material being comprised of conductive particles embedded in a matrix.
33 . The semiconductor device of claim 32 , further comprising:
a conducting layer comprising contact areas, each one of the contact areas connected with one of the vias, respectively.
34 . The semiconductor device of claim 33 , further comprising:
a solder resist layer applied above the conducting layer, the solder resist layer comprising openings above the contact areas.
35 . The semiconductor device of claim 34 , further comprising:
solder balls applied above the openings of the solder resist layer, the solder balls being electrically connected to the contact areas, respectively.Join the waitlist — get patent alerts
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