US2010025777A1PendingUtilityA1

Method for suppressing lattice defects in a semiconductor substrate

Assignee: SYNOPSYS INCPriority: Oct 30, 2007Filed: Oct 9, 2009Published: Feb 4, 2010
Est. expiryOct 30, 2027(~1.2 yrs left)· nominal 20-yr term from priority
H10P 30/21H10P 30/208H10P 30/204H10P 95/90H10D 62/364H10D 30/797H10D 30/751
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Claims

Abstract

A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for interstitial defect atoms to be emitted from the compressive layer, and in that manner energetically stable defects are formed in the lattice at a distance from the compressive layer.

Claims

exact text as granted — not AI-modified
1 . A semiconductor formed on a crystal substrate, having N-type and P-type regions, with a channel between the source and drain regions and a gate positioned above the channel, and having a depletion layer adjacent each region, comprising a compressive layer of atoms, such atoms being selected to impose a compressive stress on the crystal lattice, wherein any existing energetically stable lattice defects, lie outside the compressive layer. 
   
   
       2 . The semiconductor of  claim 1 , wherein the compressive layer atoms are larger than the lattice member atoms. 
   
   
       3 . The semiconductor of  claim 1 , wherein the compressive layer atoms are electrically neutral 
   
   
       4 . The semiconductor of  claim 1 , wherein the compressive layer is provided by co-implantation of compressive atoms with dopant atoms. 
   
   
       5 . The semiconductor of  claim 1 , wherein the compressive layer is provided by epitaxially growing the compressive layer. 
   
   
       6 . The semiconductor of  claim 1 , wherein the lattice-member atoms are silicon, and the compressive layer atoms are germanium. 
   
   
       7 . The semiconductor of  claim 1 , wherein the compressive layer lies at least partially within the depletion layer. 
   
   
       8 . The semiconductor of  claim 1 , wherein the compressive layer lies outside the depletion layer, between the depletion layer and the defects. 
   
   
       9 . The semiconductor of  claim 1 , wherein the compressive layer lies at a level shallower than that of the depletion layer, such that the defects lie in the source and drain regions.

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