DFE Margin Test Methods and Circuits that Decouple Sample and Feedback Timing

Abstract

Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter.

1 . A receiver instantiated on an integrated circuit, the receiver comprising:
 a data sampler having a sampler input and a sampler output, the data sampler to sample an input data signal to produce a series of data samples representing first and second logic values;   a multiplexer having a first input coupled to an expected data source and a second input coupled to receive a voltage node providing a voltage representative of the first logic value, and a multiplexer output; and   a path coupled between the multiplexer output and the sampler input.   
   
   
       2 . The receiver of  claim 1 , further comprising a second data sampler having a second sampler input, to receive the input data signals, and a second sampler output coupled to the first multiplexer input, the second data sampler to sample the input data signal and produce a second series of data samples on the first multiplexer input. 
   
   
       3 . The receiver of  claim 2 , further comprising a test-pattern generator coupled to a third multiplexer input to the multiplexer. 
   
   
       4 . The receiver of  claim 2 , further comprising a comparison circuit coupled to the first-mentioned sampler output and the second sampler output to compare the first-mentioned series of data samples with the second series of data samples. 
   
   
       5 . The receiver of  claim 4 , wherein the comparison circuit is to identify mismatches between corresponding samples in the first and second series of data samples, the mismatches representing sample errors. 
   
   
       6 . The receiver of  claim 5 , further comprising an accumulator coupled to an output from the comparison circuit to accumulate the sample errors. 
   
   
       7 . The receiver of  claim 6 , the comparison circuit further including a data filter to exclude some of the mismatches from representing sample errors. 
   
   
       8 . The receiver of  claim 1 , further comprising a test-pattern generator coupled to the first input to provide the expected data. 
   
   
       9 . The receiver of  claim 1 , wherein the voltage representative of the first logic value is constant over multiple clock cycles. 
   
   
       10 . The receiver of  claim 1 , wherein the multiplexer includes a third input coupled to receive a second voltage representative of the second logic value. 
   
   
       11 . The receiver of  claim 1 , further comprising an equalizer in the path between the multiplexer output and the sampler input, the equalizer to adjust the input signal responsive to expected data from the expected data source or the constant voltage representative of the first logic value. 
   
   
       12 . A method of measuring receiver error margins for an input signal applied to the receiver, the method comprising:
 sampling the input signal, using a sampler, with reference to a reference voltage and a reference timing signal to produce a series of data samples, the data samples including first samples representative of a first logic value and second samples representative of a second logic value; and   while sampling the input signal:
 applying a constant voltage representative of the first logic value to an input of an equalizer; 
 using the equalizer to equalize the input signal; and 
 reviewing the data samples for errors. 
   
   
   
       13 . The method of  claim 12 , further comprising excluding some of the data samples from error consideration. 
   
   
       14 . The method of  claim 12 , further comprising sampling the input signal with a second sampler to produce a second series of data samples. 
   
   
       15 . The method of  claim 14 , further comprising applying the second series of data samples to the input of the equalizer and using the equalizer to equalize the input signal. 
   
   
       16 . The method of  claim 12 , further comprising applying a test pattern to the input of the equalizer. 
   
   
       17 . The method of  claim 12 , further comprising adjusting the reference voltage during the sampling and correlating the errors to the reference voltage. 
   
   
       18 . The method of  claim 12 , further comprising adjusting the timing reference during the sampling and correlating the errors to the timing reference. 
   
   
       19 . The method of  claim 12 , further comprising, while sampling the input signal, applying expected data to the input of the equalizer. 
   
   
       20 . The method of  claim 19 , further comprising sampling the input signal, using a second sampler, to produce a second series of data samples, wherein the second series of data samples include the expected data. 
   
   
       21 . The method of  claim 19 , further comprising generating the expected data with a test-pattern generator. 
   
   
       22 . The method of  claim 19 , further comprising, while sampling the input signal, applying a second constant voltage representative of the second logic value to the input of the equalizer. 
   
   
       23 . An integrated circuit comprising:
 a sampler having a sampler input for receiving a input signal, the sampler for sampling the input signal to produce a series of data samples;   an equalizer having an output coupled to the sampler input and having an equalizer input, the equalizer to modify the input signal responsive to expected data signals on the equalizer input; and   a multiplexer having a multiplexer output, coupled to the equalizer input, and a plurality of multiplexer inputs to receive the expected data.   
   
   
       24 . The integrated circuit of  claim 23 , further comprising a pattern generator to produce the expected data. 
   
   
       25 . The integrated circuit of  claim 23 , wherein one of the multiplexer inputs is connected to a voltage node providing, as the expected data, a constant voltage representative of a logic value. 
   
   
       26 . The integrated circuit of  claim 23 , further comprising an error detector coupled to an output of the sampler to identify erroneous one of the data samples. 
   
   
       27 . The integrated circuit of  claim 26 , further comprising a data filter to exclude some of the data samples from being identified as erroneous. 
   
   
       28 . The integrated circuit of  claim 23 , further comprising a second sampler for sampling the input signal to produce the expected data as a second series of data samples.