Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth

Abstract

Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth. A novel implementation includes a wideband differential transistor pair and a cross-coupled differential transistor pair. The wideband differential transistor pair can be implemented with appropriate input and output impedances to extend its bandwidth for use in broadband applications. These two stages, (1) buffer stage (or data amplifier stage) and (2) cross-coupled differential pair stage, are both very fast operating stages. This design does not incur any increased loading to previous or subsequent stages in a device. In addition, there is no increase in the total amount of current that is required.

1 . A circuit, comprising:
 a first differential transistor having a first source, a first gate that is operative to receive a first differential input, and a first drain;   a second differential transistor having a second source that is connected to the first source, a second gate that is operative to receive a second differential input, and a second drain;   a third differential transistor having a third source, a third gate, and a third drain;   a fourth differential transistor having a fourth source that is connected to the third source, a fourth gate, and a fourth drain;   wherein the first drain, the third drain, and the fourth gate are connected at a first node that is a first differential output;   wherein the second drain, the fourth drain, and the third gate are connected at a second node that is a second differential output;   a first variable current source transistor having a fifth drain connected to the connected first source and second source, having a fifth gate, and having a fifth source that is grounded;   a second variable current source transistor having a sixth drain connected to the connected third source and fourth source, having a sixth gate, and having a sixth source that is grounded; and   a control module that is operative to adjust a delay of the circuit by adjusting a first DC bias voltage provided to the fifth gate to set a first DC bias current in the first variable current source transistor and by adjusting a second DC bias voltage provided to the sixth gate to set a second DC bias current in the second variable current source transistor.   
   
   
       2 . The circuit of  claim 1 , wherein:
 the control module that is operative to keep a sum of the first DC bias current and the second DC bias current constant.   
   
   
       3 . The circuit of  claim 1 , further comprising:
 a first inductor connected to the first gate; and   a second inductor connected to the second gate.   
   
   
       4 . The circuit of  claim 1 , further comprising:
 a first impedance component whose ends are connected to the first drain and to a power supply voltage of the circuit, respectively; and   a second impedance component whose ends are connected to the second drain and to the power supply voltage of the circuit, respectively.   
   
   
       5 . The circuit of  claim 4 , wherein:
 the first impedance component includes a first output resistor and a first inductor connected in series; and   the second impedance component includes a second output resistor and a second inductor connected in series.   
   
   
       6 . The circuit of  claim 1 , further comprising:
 a first capacitor whose ends are connected to the first drain and to the second gate, respectively; and   a second capacitor whose ends are connected to the second drain and to the first gate, respectively.   
   
   
       7 . The circuit of  claim 1 , wherein:
 the sum of the first DC bias current and the second DC bias current being constant keeps a DC level of the first differential output and the second differential output constant.   
   
   
       8 . The circuit of  claim 1 , wherein:
 the delay of the circuit is a function of a ratio of the first DC bias current divided by the sum of the first DC bias current and the second DC bias current.   
   
   
       9 . The circuit of  claim 1 , wherein:
 the circuit is one delay cell of a plurality of delay cells implemented within an n-tap finite impulse response (FIR) filter.   
   
   
       10 . The circuit of  claim 1 , further comprising:
 a flip-flop (FF); and wherein:   the first node and the second node are connected to an input of a FF; and   the FF is operative to receive a clock signal.   
   
   
       11 . The circuit of  claim 1 , wherein:
 the first differential transistor, the second differential transistor, the third differential transistor, the fourth differential transistor, the first variable current source, and the second variable current source are NMOS (Negative-Channel Metal-Oxide Semiconductor) transistors.   
   
   
       12 . A circuit, comprising:
 a first differential transistor having a first source, a first gate, and a first drain;   a second differential transistor having a second source that is connected to the first source, a second gate, and a second drain;   a first inductor whose ends are connected to a first differential input and to the first gate, respectively;   a second inductor whose ends are connected to a second differential input and to the second gate, respectively;   a third differential transistor having a third source, a third gate, and a third drain;   a fourth differential transistor having a fourth source that is connected to the third source, a fourth gate, and a fourth drain;   wherein the first drain, the third drain, and the fourth gate are connected at a first node that is a first differential output;   wherein the second drain, the fourth drain, and the third gate are connected at a second node that is a second differential output;   a first variable current source transistor having a fifth drain connected to the connected first source and second source, having a fifth gate, and having a fifth source that is grounded;   a second variable current source transistor having a sixth drain connected to the connected third source and fourth source, having a sixth gate, and having a sixth source that is grounded; and   a control module that is operative to:
 adjust a delay of the circuit by adjusting a first DC bias voltage provided to the fifth gate to set a first DC bias current in the first variable current source transistor and by adjusting a second DC bias voltage provided to the sixth gate to set a second DC bias current in the second variable current source transistor; 
 the control module that is operative to keep a sum of the first DC bias current and the second DC bias current constant. 
   
   
   
       13 . The circuit of  claim 12 , further comprising:
 a first impedance component whose ends are connected to the first drain and to a power supply voltage of the circuit, respectively; and   a second impedance component whose ends are connected to the second drain and to the power supply voltage of the circuit, respectively.   
   
   
       14 . The circuit of  claim 13 , wherein:
 the first impedance component includes a first output resistor and a first inductor connected in series; and   the second impedance component includes a second output resistor and a second inductor connected in series.   
   
   
       15 . The circuit of  claim 12 , further comprising:
 a first capacitor whose ends are connected to the first drain and to the second gate, respectively; and   a second capacitor whose ends are connected to the second drain and to the first gate, respectively.   
   
   
       16 . The circuit of  claim 12 , wherein:
 the sum of the first DC bias current and the second DC bias current being constant keeps a DC level of the first differential output and the second differential output constant.   
   
   
       17 . The circuit of  claim 12 , wherein:
 the delay of the circuit is a function of a ratio of the first DC bias current divided by the sum of the first DC bias current and the second DC bias current.   
   
   
       18 . A circuit, comprising:
 a first differential transistor having a first source, a first gate that is operative to receive a first differential input, and a first drain;   a second differential transistor having a second source that is connected to the first source, a second gate that is operative to receive a second differential input, and a second drain;   a first capacitor whose ends are connected to the first drain and to the second gate, respectively;   a second capacitor whose ends are connected to the second drain and to the first gate, respectively;   a third differential transistor having a third source, a third gate, and a third drain;   a fourth differential transistor having a fourth source that is connected to the third source, a fourth gate, and a fourth drain;   wherein the first drain, the third drain, and the fourth gate are connected at a first node that is a first differential output;   wherein the second drain, the fourth drain, and the third gate are connected at a second node that is a second differential output;   a first variable current source transistor having a fifth drain connected to the connected first source and second source, having a fifth gate, and having a fifth source that is grounded;   a second variable current source transistor having a sixth drain connected to the connected third source and fourth source, having a sixth gate, and having a sixth source that is grounded; and   a control module that is operative to:
 adjust a delay of the circuit by adjusting a first DC bias voltage provided to the fifth gate to set a first DC bias current in the first variable current source transistor and by adjusting a second DC bias voltage provided to the sixth gate to set a second DC bias current in the second variable current source transistor; and 
 keep a sum of the first DC bias current and the second DC bias current constant thereby keeping a DC level of the first differential output and the second differential output constant; and wherein: 
   the delay of the circuit is a function of a ratio of the first DC bias current divided by the sum of the first DC bias current and the second DC bias current.   
   
   
       19 . The circuit of  claim 18 , further comprising:
 a first impedance component whose ends are connected to the first drain and to a power supply voltage of the circuit, respectively; and   a second impedance component whose ends are connected to the second drain and to the power supply voltage of the circuit, respectively.   
   
   
       20 . The circuit of  claim 18 , wherein:
 the first differential transistor, the second differential transistor, the third differential transistor, the fourth differential transistor, the first variable current source, and the second variable current source are NMOS (Negative-Channel Metal-Oxide Semiconductor) transistors.