Embedded chip substrate and fabrication method thereof

Abstract

An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.

1 . An embedded chip substrate, comprising:
 a first insulation layer;   a core layer, disposed on the first insulation layer and having an opening for exposing a portion of the first insulation layer;   a chip, adhered into a recess formed by the opening and the first insulation layer;   a second insulation layer, disposed on the core layer for covering the chip;   a first circuit layer, disposed at the outer side of the first insulation layer, the first insulation layer being disposed between the first circuit layer and the core layer; and   a second circuit layer, disposed at the outer side of the second insulation layer, wherein the second insulation layer is located between the second circuit layer and the core layer, the first circuit layer is electrically connected to the second circuit layer, and the second circuit layer is electrically connected to the chip.   
     
     
         2 . The embedded chip substrate as claimed in  claim 1 , wherein a material of the first insulation layer comprises a two-stage curable compound. 
     
     
         3 . The embedded chip substrate as claimed in  claim 1 , wherein a material of the second insulation layer comprises a two-stage curable compound. 
     
     
         4 . The embedded chip substrate as claimed in  claim 1 , further comprising:
 a bottom adhesion layer, disposed on the first insulation layer in the recess and located between the chip and the first insulation layer.   
     
     
         5 . The embedded chip substrate as claimed in  claim 4 , further comprising:
 a side wall adhesion layer, disposed between the inner side wall of the recess and the side wall of the chip.   
     
     
         6 . The embedded chip substrate as claimed in  claim 1 , further comprising:
 a side wall adhesion layer, disposed between the inner side wall of the recess and the side wall of the chip.   
     
     
         7 . The embedded chip substrate as claimed in  claim 1 , wherein the first insulation layer is extended between the inner side wall of the recess and the side wall of the chip. 
     
     
         8 . The embedded chip substrate as claimed in  claim 1 , further comprising:
 a plurality of conductive blind vias, penetrating the second insulation layer and electrically connected to the second circuit layer and the chip.   
     
     
         9 . The embedded chip substrate as claimed in  claim 1 , further comprising:
 a plurality of conductive through holes, penetrating the second insulation layer, the core layer, and the first insulation layer and electrically connected to the first circuit layer and the second circuit layer.   
     
     
         10 . The embedded chip substrate as claimed in  claim 1 , wherein the core layer comprises:
 a core dielectric layer; and   two core circuit layers, respectively disposed at opposite sides of the core layer.   
     
     
         11 . The embedded chip substrate as claimed in  claim 1 , further comprising:
 two build-up structures, respectively disposed at the outer side of the second insulation layer and the outer side of the first insulation layer, a plurality of solder pads being located at the outer sides of the two build-up structures, respectively.   
     
     
         12 . The embedded chip substrate as claimed in  claim 11 , further comprising:
 two solder mask layers, respectively disposed at the outer sides of the build-up structures and respectively exposing the corresponding solder pads.   
     
     
         13 . A fabrication method of an embedded chip substrate, the fabrication method comprising: providing a core layer that has an opening;
 providing a first insulation layer and a first conductive layer, the first conductive layer being disposed on the first insulation layer;   disposing the core layer on the first insulation layer, the first insulation layer being located between the core layer and the first conductive layer;   adhering a chip into a recess formed by the opening and the first insulation layer;   providing a second insulation layer and a second conductive layer, the second conductive layer being disposed on the second insulation layer;   disposing the second insulation layer on the core layer, the second insulation layer being located between the core layer and the second conductive layer and covering the recess;   laminating the first conductive layer, the first insulation layer, the core layer, the second insulation layer, and the second conductive layer; and   respectively patterning the first conductive layer and the second conductive layer, so as to form a first circuit layer and a second circuit layer, wherein the first circuit layer is electrically connected to the second circuit layer, and the second circuit layer is electrically connected to the chip.   
     
     
         14 . The fabrication method of the embedded chip substrate as claimed in  claim 13 , further comprising:
 forming a plurality of conductive blind vias penetrating the second insulation layer before the first conductive layer is patterned, such that the chip is electrically connected to the second conductive layer.   
     
     
         15 . The fabrication method of the embedded chip substrate as claimed in  claim 13 , further comprising:
 forming a plurality of conductive through holes penetrating the second insulation layer, the core layer, and the first insulation layer after the first conductive layer and the second conductive layer are patterned, such that the first circuit layer is electrically connected to the second circuit layer.   
     
     
         16 . The fabrication method of the embedded chip substrate as claimed in  claim 13 , further comprising:
 heating the first insulation layer in the step of laminating the first conductive layer, the first insulation layer, the core layer, the second insulation layer, and the second conductive layer, such that the first insulation layer overflows between the side wall of the chip and the inner side wall of the recess.   
     
     
         17 . The fabrication method of the embedded chip substrate as claimed in  claim 13 , wherein a method of adhering the chip into the recess comprises:
 disposing a bottom adhesion layer on the first insulation layer that is located in the recess; and   disposing the chip on the bottom adhesion layer.   
     
     
         18 . The fabrication method of the embedded chip substrate as claimed in  claim 17 , wherein the method of adhering the chip into the recess further comprises:
 forming a side wall adhesion layer between the inner side wall of the recess and the side wall of the chip.   
     
     
         19 . The fabrication method of the embedded chip substrate as claimed in  claim 13 , wherein a method of adhering the chip into the recess comprises:
 forming a side wall adhesion layer between the inner side wall of the recess and the side wall of the chip.   
     
     
         20 . The fabrication method of the embedded chip substrate as claimed in  claim 13 , further comprising:
 respectively forming a build-up structure at the outer side of the first insulation layer and the outer side of the second insulation layer, a plurality of solder pads being located at the outer sides of the two build-up structures, respectively.