Error correction code striping

Abstract

A method is disclosed which decreases the amount of error correction code data required to detect and correct errors in digital data while still maintaining a specified ability to correct errors in large groups of contiguous data. The present invention accomplishes this by placing distance either in space or in time between bytes grouped mathematically for error correction code calculations. An error affecting contiguous bytes, like scratches or other defects in digital storage media, or certain types of interference in either wired or wireless digital communications, would affect many error correction code groups, but would only affect one byte from each group. The error can easily be corrected using only a one dimensional error correction code, removing the need for a two dimensional product error correction code and the additional data overhead that the column ECC data necessarily adds to the block.

1 . A method comprising:
 receiving user data in a first ordered manner;   organizing said user data into rows and columns;   calculating ECC data for each of said rows;   appending said ECC data to each of said rows wherein the ECC data calculated for a given of said rows is appended to that specific given of said rows; and   sending combined user data and ECC data in a second ordered manner.   
   
   
       2 . The method of  claim 1 , wherein receiving user data comprises receiving user data having an initial set of ECC data included therein. 
   
   
       3 . The method of  claim 1  wherein the step of sending combined user data and ECC data comprises sending combined user data and ECC data column by column. 
   
   
       4 . An encoder comprising:
 a memory receiving sets of data in a first ordered manner, the memory storing the sets of data in rows and columns wherein each of the sets of data is stored in a different one of the rows from the other of the sets of data;   an ECC data generator coupled to the memory, the ECC data generator generating ECC data for each of the sets of data in each of the rows and appending the generated ECC data to the set of data for its respective row; and   a device coupled to the memory, the device extracting the combined sets of data and ECC data in a second ordered manner.   
   
   
       5 . The encoder of  claim 4  wherein the device extracts the combined sets of data and ECC data column by column. 
   
   
       6 . The encoder of  claim 4 , wherein the device coupled to the memory consists of a modulator which modulates the combined sets of data and ECC data for a specific channel. 
   
   
       7 . The encoder of  claim 4 , wherein each set of data has an initial set of ECC data included therein. 
   
   
       8 . The encoder of  claim 4 , wherein the memory is also part of a decoder. 
   
   
       9 . A decoder comprising:
 a first device extracting data encoded in a first ordered manner;   a memory coupled to the first device receiving the encoded data, the memory storing the data in rows and columns in a second ordered manner such that each of the rows contain a set of data and ECC data calculated for the set of data;   an ECC decoder and data corrector coupled to the memory, the ECC decoder and data corrector receiving the data from the memory in the second ordered manner, using the ECC data to correct errors in the set of data, and sending the error corrections to the memory; and   a second device coupled to the memory, the second device extracting the sets of data in the second ordered manner.   
   
   
       10 . The decoder of  claim 9 , wherein the first ordered manner is column by column. 
   
   
       11 . The decoder of  claim 9 , wherein the first device is a demodulator which demodulates the data from a specific channel. 
   
   
       12 . The decoder of  claim 9 , wherein each set of data has an initial set of ECC data included therein. 
   
   
       13 . The decoder of  claim 9 , wherein the memory is also part of an encoder circuit.