Semiconductor Device, an Electronic Device and a Method for Operating the Same

Abstract

A semiconductor memory device includes circuitry coupled to a plurality of memory cells with transistors. The circuitry is configured to change a potential of a body of the transistor to a degree depending on a charging state of the body. A gate electrode of the transistor is maintained in a non-addressed state.

1 . A semiconductor memory device comprising:
 a plurality of memory cells, wherein each of the memory cells comprises a transistor, and each transistor includes a gate electrode and first and second doped portions;   wordlines coupled to gate electrodes of the transistors;   bitlines coupled to first doped portions of the transistors;   source lines coupled to second doped portions of the transistors; and   circuitry coupled to the memory cells, wherein the circuitry is configured to perform a self-refresh operation of the memory device while substantially maintaining a voltage applied to the wordlines.   
   
   
       2 . The semiconductor memory device of  claim 1 , wherein the circuitry further comprises data sensing circuitry coupled to the plurality of memory cells, the data sensing circuitry being configured to determine data states of the memory cells. 
   
   
       3 . The semiconductor memory device of  claim 2 , wherein each transistor comprises an electrically floating body transistor configured to generate a current between the first and second doped portions that is representative of a data state of the respective memory cell, and the current is generated in response to a read control signal transmitted by the data sensing circuitry. 
   
   
       4 . The semiconductor memory device of  claim 1 , wherein the circuitry is configured to apply a predetermined potential difference between a selected bitline and a selected source line. 
   
   
       5 . The semiconductor memory device of  claim 1 , wherein the transistor of each memory cell is an N-channel type transistor. 
   
   
       6 . The semiconductor memory device of  claim 1 , wherein the electrically floating body transistor of each memory cell is a P-channel type transistor. 
   
   
       7 . A semiconductor memory device comprising:
 a plurality of memory cells, each of the memory cells comprising a transistor;   wordlines coupled to gate electrodes of the transistors;   bitlines coupled to first doped portions of the transistors;   source lines coupled to second doped portions of the transistors; and   circuitry coupled to the memory cells, wherein the circuitry is configured to perform a self-refresh operation of all the memory cells being coupled to at least one source line or to at least one bitline.   
   
   
       8 . The semiconductor memory device of  claim 7 , wherein the circuitry is configured to apply a predetermined voltage to at least one of the source lines or to at least one of the bitlines. 
   
   
       9 . A semiconductor memory device comprising:
 a plurality of memory cells, each of the memory cells including a transistor; and   circuitry coupled to the memory cells, wherein the circuitry is configured to change a potential of a body of the transistor of each memory cell to a degree depending on a charging state of the body while maintaining a gate electrode of the transistor in a non-addressed state.