US2010013022A1PendingUtilityA1

Semiconductor device with multiple gate dielectric layers and method for fabricating the same

Assignee: HYNIX SEMICONDUCTOR INCPriority: Dec 29, 2004Filed: Jun 15, 2009Published: Jan 21, 2010
Est. expiryDec 29, 2024(expired)· nominal 20-yr term from priority
H10D 64/01344H10P 10/00H10P 14/60H10D 64/693H10D 84/0181H10D 84/0177H10D 84/038H10D 84/0119H10B 12/09H10B 12/05
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Claims

Abstract

Disclosed are a semiconductor device with dual gate dielectric layers and a method for fabricating the same. The semiconductor device includes: a silicon substrate divided into a cell region where NMOS transistors are formed and a peripheral region where NMOS and PMOS transistors are formed; a targeted silicon oxide layer formed on the silicon substrate in the cell region; an oxynitride layer formed on the silicon substrate in the peripheral region; a first gate structure formed in the cell region; a second gate structure formed on the oxynitride layer in an NMOS region of the peripheral region; and a third gate structure formed on the oxynitride layer in a PMOS region of the peripheral region.

Claims

exact text as granted — not AI-modified
1 . A semiconductor memory device, comprising:
 a silicon substrate comprising a cell region where NMOS transistors are formed and a peripheral region where NMOS and PMOS transistors are formed;   a targeted silicon oxide layer on the silicon substrate in the cell region;   an oxynitride layer on the silicon substrate in the peripheral region;   a first gate structure formed on the targeted silicon layer and including an n+-type silicon electrode, a low resistance metal electrode, and a gate hard mask;   a second gate structure formed on the oxynitride layer in an NMOS region of the peripheral region and including an n+-type silicon electrode, a low resistance metal electrode, and a gate hard mask; and   a third gate structure formed on the oxynitride layer in a PMOS region of the peripheral region and including a p+-type silicon electrode, a low resistance metal electrode, and a gate hard mask.   
   
   
       2 . The semiconductor device of  claim 1 , wherein the targeted silicon oxide layer has a thickness greater than that of the oxynitride layer. 
   
   
       3 . The semiconductor device of  claim 1 , wherein the oxynitride layer is formed by oxidizing a surface portion of the silicon substrate on which silicon-nitrogen bonds are formed and the targeted silicon oxide layer is formed by oxidizing a silicon oxide layer formed on the silicon substrate and on which silicon-oxygen-nitrogen bonds are formed. 
   
   
       4 . The semiconductor device of  claim 1 , wherein the oxynitride layer contains nitrogen of a concentration ranging from approximately 5% to approximately 30% in atomic percent. 
   
   
       5 . The semiconductor device of  claim 1 , wherein the n+-type silicon electrode is formed by ion implanting one of phosphorus and arsenic. 
   
   
       6 . The semiconductor device of  claim 1 , wherein the p+-type silicon electrode is formed by ion implanting one of boron, boron fluoride and boron difluoride.

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