Non-volatile memory cell with a hybrid access transistor

Abstract

An integrated circuit (IC) is disclosed. The IC comprises a substrate with a cell region defined thereon. The cell region comprises a thin gate doped well tailored for transistors with thin gate dielectric layers. The IC also includes a non-volatile memory cell in the cell region. The non-volatile memory cell has an access transistor and a storage transistor. The access transistor includes an access gate with an access gate dielectric comprising a thick gate dielectric layer on the thin gate doped well. Wells for transistors with thick gate dielectric layers have a lower dopant concentration than the thin gate doped well.

1 . An integrated circuit (IC) comprising:
 a substrate with a cell region defined thereon, the cell region comprises a thin gate doped well tailored for transistors with thin gate dielectric layers; and   a non-volatile memory cell in the cell region, the non-volatile memory cell having an access transistor and a storage transistor, wherein the access transistor includes an access gate with an access gate dielectric comprising a thick gate dielectric layer on the thin gate doped well, wherein wells for transistors with thick gate dielectric layers have a lower dopant concentration than the thin gate doped well.   
   
   
       2 . The IC of  claim 1  wherein the storage transistor comprises:
 a storage gate in a storage portion of the cell region, the storage gate comprises a storage layer and a storage gate electrode over the storage layer; and   first and second storage diffusion regions adjacent to the storage gate.   
   
   
       3 . The IC of  claim 1  wherein the access transistor comprises:
 the access gate comprising the access gate dielectric and an access gate electrode over the thick gate dielectric layer; and   first and second access diffusion regions adjacent to the access gate.   
   
   
       4 . The IC of  claim 1  wherein the memory cell comprises:
 a storage layer in a storage portion of the cell region;   the access gate dielectric in an access portion of the cell region; and   a gate electrode layer over the storage layer and thick gate dielectric layer.   
   
   
       5 . The IC of  claim 4  wherein the memory cell comprises a storage gate and the access gate over the cell region, wherein the storage gate comprises a gate electrode formed from patterning the gate electrode layer over the storage layer and the access gate comprises an access gate electrode formed from patterning the gate electrode layer over the access gate dielectric. 
   
   
       6 . The IC of  claim 5  comprises first and second access diffusion regions adjacent to the access gate and first and second storage diffusion regions adjacent to the storage gate. 
   
   
       7 . The IC of  claim 6  includes a common diffusion region comprising one of the access diffusion regions is adjacent to the storage gate and one of the storage diffusion regions is adjacent to the access gate. 
   
   
       8 . The IC of  claim 4  wherein the storage layer comprises a composite storage layer. 
   
   
       9 . The IC of  claim 4  wherein the storage layer comprises a composite storage layer comprising an oxide-nitride-oxide stack. 
   
   
       10 . The IC of  claim 1  wherein:
 the thin gate doped well comprises n-type dopants and the transistors comprise p-type transistors; or   the thin gate doped well comprises p-type dopants and the transistors comprise n-type transistors.   
   
   
       11 . The IC of  claim 1  wherein the thin gate doped well comprises a dopant concentration of about E17-E19 cm −3 . 
   
   
       12 . The IC of  claim 1  wherein the thick access gate dielectric is about 30-80 Å thick. 
   
   
       13 . A device comprising:
 a substrate with an active region prepared with a thin gate doped cell well tailored for transistors with thin gate dielectric; and   a transistor in the active region on the thin gate doped well, wherein the transistor comprises a gate having a gate electrode over a thick gate dielectric.   
   
   
       14 . The device of  claim 13  wherein:
 the thin gate doped well comprises n-type dopants and the transistor comprises a p-type transistor; or   the thin gate doped well comprises p-type dopants and the transistor comprises a n-type transistor.   
   
   
       15 . The device of  claim 13  wherein the thin gate doped well comprises a dopant concentration of about E17-E19 cm −3 . 
   
   
       16 . The device of  claim 13  wherein the active region comprises a cell region of a memory cell. 
   
   
       17 . The device of  claim 16  wherein the memory cell comprises:
 an access transistor having an access gate electrode over a thick access gate dielectric; and   a storage transistor coupled to the access transistor, the storage transistor having a storage gate electrode over a storage gate dielectric.   
   
   
       18 . The device of  claim 17  wherein the storage gate dielectric comprises an ONO storage stack. 
   
   
       19 . The device of  claim 17  wherein the thick access gate dielectric is about 30-80 Å thick. 
   
   
       20 . A device comprising:
 a substrate with a cell region defined thereon, the cell region comprises a thin gate doped well tailored for transistors with thin gate dielectric layers; and   first and second transistors disposed in the cell region, wherein the first transistor includes a first gate with a first gate dielectric comprising a thick gate dielectric layer on the thin gate doped well.   
   
   
       21 . The device of  claim 20  wherein the cell region comprises a memory cell. 
   
   
       22 . The device of  claim 20  wherein:
 the thin gate doped well comprises n-type dopants and the transistors comprise p-type transistors; or   the thin gate doped well comprises p-type dopants and the transistors comprise n-type transistors.   
   
   
       23 . The device of  claim 20  wherein:
 the first transistor comprises an access transistor having an access gate electrode over the first thick gate dielectric; and   the second transistor comprises a storage transistor coupled to the access transistor, the storage transistor having a storage gate electrode over a storage gate dielectric.   
   
   
       24 . The device of  claim 20  wherein the thin gate doped well comprises a dopant concentration of about E17-E19 cm −3 . 
   
   
       25 . The device of  claim 23  wherein the storage gate dielectric comprises a composite storage layer.