Flash memory device with stacked dielectric structure including zirconium oxide and method for fabricating the same

Abstract

A dielectric structure disposed between a floating gate and a control gate of a flash memory device includes: a first dielectric layer; a third dielectric layer having a k-dielectric constant substantially the same as that of the first dielectric layer; and a second dielectric layer disposed between the first dielectric layer and the third dielectric layer, having a greater k-dielectric constant than that of the first and third dielectric layers and formed by alternately and repeatedly stacking a plurality of aluminum oxide (Al 2 O 3 ) layers and a plurality of zirconium oxide (ZrO 2 ) layers.

1 . A non-volatile memory device, comprising:
 a floating gate provide over a substrate;   a control gate provided over the floating gate; and   a dielectric structure provided between the floating gate and the control gate, the dielectric structure including:
 a first dielectric layer; 
 a second dielectric layer formed over the first dielectric layer and having a k-dielectric constant greater than that of the first dielectric layer, the second dielectric layer including a plurality of aluminum oxide (Al 2 O 3 ) layers and a plurality of zirconium oxide (ZrO 2 ) layers; and 
 a third dielectric layer formed over the second dielectric layer. 
   
   
   
       2 . The device of  claim 1 , wherein a first Al 2 O 3  layer and a last Al 2 O 3  layer contact the first dielectric layer and the third dielectric layer, respectively,
 wherein the third dielectric layer has a k-dielectric constant substantially the same as that of the first dielectric layer.   
   
   
       3 . The device of  claim 1 , wherein a first Al 2 O 3  layer and a third Al 2 O 3  layer contact the first dielectric layer and the third dielectric layer, respectively, and
 wherein the second dielectric layer comprises the first Al 2 O 3  layer, a first ZrO 2  layer, a second Al 2 O 3  layer, a second ZrO 2  layer, and the third Al 2 O 3  layer.   
   
   
       4 . The device of  claim 3 , wherein the first dielectric layer and the third dielectric layer comprise a silicon oxide (SiO 2 ) layer. 
   
   
       5 . The device of  claim 4 , wherein a total thickness of the dielectric structure from the first dielectric layer to the third dielectric layer ranges from approximately 50 Å to approximately 200 Å. 
   
   
       6 . A flash memory device, comprising:
 a substrate;   a tunnel oxide layer formed over the substrate;   a floating gate formed over the tunnel oxide layer;   a first dielectric layer formed over the floating gate;   a second dielectric layer over the first dielectric layer and formed by alternately stacking a aluminum oxide (Al 2 O 3 ) layer and a zirconium oxide (ZrO 2 ) layer, so that the second dielectric layer has at least five different layers, the second dielectric layer having a greater k-dielectric constant than that of the first dielectric layer;   a third dielectric layer formed over the second dielectric layer; and   a control gate formed over the third dielectric layer.   
   
   
       7 . The flash memory device of  claim 6 , wherein the Al 2 O 3  layers and the ZrO 2  layers of the second dielectric layer are stacked such that a first Al 2 O 3  layer and a third Al 2 O 3  layer contact the first dielectric layer and with the third dielectric layer, respectively, and
 wherein the third dielectric layer having a k-dielectric constant substantially the same as that of the first dielectric layer.   
   
   
       8 . The flash memory device of  claim 6 , wherein the Al 2 O 3  layers and the ZrO 2  layers of the second dielectric layer are stacked such that a first Al 2 O 3  layer and a last Al 2 O 3  layer contact the first dielectric layer and with the third dielectric layer, respectively,
 wherein the third dielectric layer having a k-dielectric constant substantially the same as that of the first dielectric layer, and   wherein the second dielectric layer comprises the first Al 2 O 3  layer, a first ZrO 2  layer, a second Al 2 O 3  layer, a second ZrO 2  layer, and the last Al 2 O 3  layer.   
   
   
       9 . The flash memory device of  claim 8 , wherein the first dielectric layer and the third dielectric layer comprise a SiO 2  layer. 
   
   
       10 . The flash memory device of  claim 9 , wherein a total thickness of the first dielectric layer, the second dielectric layer, and the third dielectric layer ranges from approximately 50 Å to approximately 200 Å.