Tft-lcd array substrate and manufacturing method thereof

Abstract

A liquid crystal display (LCD) array substrate and a manufacturing method thereof are provided. The manufacturing method comprises depositing a semiconductor layer, a doped semiconductor layer and a metal film for source and drain electrodes sequentially on a base substrate and then forming a data line, a source electrode, a drain electrode and a thin film transistor (TFT) channel region by a first patterning process; depositing a first insulating film and a gate metal film sequentially and then forming a gate line and a gate electrode by a second patterning process and forming an insulating layer via hole in the first insulating layer above the drain electrode; depositing a transparent conductive film and then forming a pixel electrode by a third patterning process; and forming a second insulating layer.

1 . A liquid crystal display (LCD) array substrate comprising a gate line, a data line, a pixel electrode, and a thin film transistor, wherein the thin film transistor comprises:
 a semiconductor layer and a doped semiconductor layer formed on a base substrate sequentially;   a source electrode and a drain electrode formed on the doped semiconductor layer, wherein a thin film transistor (TFT) channel region is formed between the source electrode and the drain electrode and the source electrode is connected with the data line;   a first insulating layer formed on the source electrode and the drain electrode, in which an insulating layer via hole is formed so that the pixel electrode is connected with the drain electrode through the insulating layer via hole;   a gate electrode formed on the first insulating layer and positioned above the TFT channel region, wherein the gate electrode is connected with the gate line; and   a second insulating layer formed on the gate line and the gate electrode.   
     
     
         2 . The LCD array substrate according to  claim 1 , wherein a light-shielding layer is further formed between the base substrate and the semiconductor layer. 
     
     
         3 . A liquid crystal display (LCD) array substrate comprising a gate line, a data line, a pixel electrode and a thin film transistor, wherein the thin film transistor comprises:
 a semiconductor layer and a doped semiconductor layer formed on a base substrate sequentially;   a source electrode and a drain electrode formed on the doped semiconductor layer, wherein a thin film transistor (TFT) channel region is formed between the source electrode and the drain electrode and the source electrode is connected with the data line;   a first insulating layer formed on the source electrode and the drain electrode, in which an insulating layer via hole is formed so that the pixel electrode is connected with the drain electrode through the insulating layer via hole; and   a gate electrode formed on the first insulating layer and positioned above the TFT channel region, wherein the gate electrode is connected with the gate line and an insulating metal oxide film is formed on the surface of the gate line and the gate electrode by an oxidation process.   
     
     
         4 . The LCD array substrate according to  claim 1 , wherein a light-shielding layer is further formed between the substrate and the semiconductor layer. 
     
     
         5 . A method for manufacturing a liquid crystal display (LCD) array substrate comprising:
 step 1 of depositing a semiconductor layer, a doped semiconductor layer and a metal film for source and drain electrodes sequentially on a base substrate and then forming a data line, a source electrode, a drain electrode and a thin film transistor (TFT) channel region by a first patterning process;   step 2 of depositing a first insulating film and a gate metal film sequentially on the substrate after the step 1 and then forming a gate line and a gate electrode by a second patterning process, wherein an insulating layer via hole is formed in the first insulating layer above the drain electrode, and the gate electrode is positioned above the TFT channel region;   step 3 of depositing a transparent conductive film on the substrate after the step 2 and then forming a pixel electrode by a third patterning process, wherein the pixel electrode is connected with the drain electrode through the insulating layer via hole; and   step 4 of forming a second insulating layer on the substrate after the step 3 to cover the gate line and gate electrode.   
     
     
         6 . The method according to  claim 5 , wherein the step 2 comprises:
 step 21 of depositing the first insulating layer on the substrate after step 1 and then depositing the gate metal film;   step 22 of applying a photoresist layer on the gate metal film;   step 23 of performing an exposure and development process so that the photoresist layer is formed into a completely removed region, a partially remained region and a completely remained region, wherein the region where the gate line and the gate electrode are to be formed corresponds to the completely remained region, the region where the insulating layer via hole is to be formed above the drain electrode corresponds to the completely removed region, and the remaining region on the substrate corresponds to the partially remained region;   step 24 of performing a first etching process so that the gate metal film at a position corresponding to the insulating layer via hole is completely removed and the first insulating layer at this position is partially removed in the thickness direction;   step 25 of performing an ashing process to completely remove the photoresist in the partially remained region;   step 26 of performing a second etching process to form the gate line and the gate electrode; and   step 27 of performing a third etching process so that the first insulating layer at the position corresponding to the insulating layer via hole is completely removed and the drain electrode is exposed.   
     
     
         7 . The method according to  claim 5 , wherein the step 4 comprises:
 depositing the second insulating layer on the substrate on which the remained photoresist is not removed after forming the pixel electrode so that the substrate is entirely covered by the second insulating layer, and then removing the second insulating layer on the photoresist along with the photoresist by a lifting-off process.   
     
     
         8 . The method according to  claim 6 , wherein the step 4 comprises:
 depositing the second insulating layer on the substrate on which the remained photoresist is not removed after forming the pixel electrode so that the substrate is entirely covered by the second insulating layer, and then removing the second insulating layer on the photoresist along with the photoresist by a lifting-off process.   
     
     
         9 . The method according to  claim 5 , wherein the step 4 comprises:
 performing a process for removing the remained photoresist after forming the pixel electrode, and then oxidizing the exposed surface of the gate electrode and the gate lines so that an insulating metal oxide film is formed.   
     
     
         10 . The method according to  claim 6 , wherein the step 4 comprises:
 performing a process for removing the remained photoresist after forming the pixel electrode, and then oxidizing the exposed surface of the gate electrode and the gate lines so that an insulating metal oxide film is formed.   
     
     
         11 . The method according to  claim 5 , wherein a light-shielding layer is deposited on the substrate prior to depositing the semiconductor layer in the step 1. 
     
     
         12 . The method according to  claim 6 , wherein a light-shielding layer is deposited on the substrate prior to depositing the semiconductor layer in the step 1. 
     
     
         13 . The method according to  claim 7 , wherein a light-shielding layer is deposited on the substrate prior to depositing the semiconductor layer in the step 1. 
     
     
         14 . The method according to  claim 8 , wherein a light-shielding layer is deposited on the substrate prior to depositing the semiconductor layer in the step 1. 
     
     
         15 . The method according to  claim 9 , wherein a light-shielding layer is deposited on the substrate prior to depositing the semiconductor layer in the step 1. 
     
     
         16 . The method according to  claim 10 , wherein a light-shielding layer is deposited on the substrate prior to depositing the semiconductor layer in the step 1.