Data processing device with instruction translator and memory interface device to translate non-native instructions into native instructions for processor

Abstract

A data processing device includes a processor core, and a memory interface portion arranged between the processor core and an external memory mapped into a predetermined external memory space. The memory interface portion includes a fetch circuit for receiving an address value for access to the external memory space from the processor core, and fetching the data at the address in the external memory, a translator for translating the normative instruction fetched from the external memory into the native instruction, and a select circuit for selectively applying the data read from the external memory space and the instruction prepared by translating the instruction read from the external memory space by the translator to the processor core depending on whether the address value for the access to the external memory space is in a predetermined region or not.

1 - 18 . (canceled) 
     
     
         19 . A data processing apparatus comprising:
 a central processing unit; and   an instruction memory,   wherein said central processing unit comprises a memory interface unit, an instruction register for fetching an instruction code containing plural instructions stored in said instruction memory, a plurality of instruction decoders, and a plurality of execution units each of which executes the instruction decoded by corresponding instruction decoder,   wherein said memory interface unit comprises an instruction translating unit, and determines whether translating said instruction code fetched from said instruction memory for translating said instruction code from a first instruction format having one byte length to a second instruction format having plural byte length in accordance with an instruction fetched address of said instruction code,   wherein each of said instruction decoders decodes said instruction code provided from said instruction register, and   wherein the instruction translation during the instruction fetch by said instruction translation unit, the instruction decoding by each said instruction decoder, and the execution of the decoded instruction by said execution units are performed in pipeline manner.   
     
     
         20 . The data processing apparatus according to  claim 19 ,
 wherein said instruction memory comprises a first instruction memory and a second instruction memory, each of which is allocated to corresponding address area,   wherein said first instruction memory stores instruction codes having said first instruction format, and   wherein said second instruction memory stores instruction codes having said second instruction format.   
     
     
         21 . The data processing apparatus according to  claim 20 ,
 wherein said memory interface unit receives said instruction code from said instruction memory by byte length of said second instruction format, uses one byte of received instruction code for translating from said first instruction format to said second instruction format when said instruction code is received from said first instruction memory.