CMOS Image Sensor and Manufacturing Method Thereof
Abstract
Disclosed are a CMOS image sensor and a manufacturing method thereof. The method includes forming an isolation layer in a semiconductor substrate, defining an active region including a photo diode region and a transistor region; forming a gate insulating layer and a gate electrode on the transistor region; forming a first low-concentration diffusion region in the photo diode region; forming a second low-concentration diffusion region in the transistor region; forming an insulating layer over an entire surface of the substrate; implanting fluorine ions in an upper surface of the photo diode region; etching the insulating layer to form insulating sidewalls on sides of the gate electrode; forming a high-concentration diffusion region in the transistor region partially overlapping with the second low-concentration diffusion region; and forming a third low-concentration diffusion region on the upper surface of the photo diode region, the third low-concentration diffusion region having a conductivity type opposite to the first low-concentration diffusion region.
Claims
exact text as granted — not AI-modified1 . A CMOS image sensor including a photo diode and a MOS transistor, the photo diode comprising:
a first low-concentration diffusion region in a semiconductor substrate, having a conductivity type opposite to the substrate; and a fluorine implant layer in an upper surface of the substrate, at least partially overlapping with the first low-concentration diffusion region.
2 . The sensor of claim 1 , wherein the photo diode further comprises a second low-concentration diffusion region having a conductivity type opposite to the first low-concentration diffusion region.
3 . The sensor of claim 2 , wherein the second low-concentration diffusion region has a shallower dopant concentration profile than the first low-concentration diffusion region.
4 . The sensor of claim 1 , further comprising an isolation layer in the substrate a predetermined distance from the first low-concentration diffusion region.
5 . The sensor of claim 2 , further comprising an isolation layer in the substrate a predetermined distance from the first low-concentration diffusion region.
6 . The sensor of claim 1 , wherein the MOS transistor comprises a gate insulating layer and a gate electrode.
7 . The sensor of claim 6 , wherein the gate electrode comprises polysilicon and fluorine ions.
8 . The sensor of claim 2 , wherein the MOS transistor comprises a gate insulating layer and a gate electrode.
9 . The sensor of claim 8 , wherein the gate electrode comprises polysilicon and fluorine ions.
10 . The sensor of claim 6 , further comprising insulating sidewalls on sides of the gate electrode.
11 . The sensor of claim 10 , wherein the insulating sidewalls comprise at least one of a nitride and a TEOS oxide.
12 . The sensor of claim 11 , wherein the insulating sidewalls comprise fluorine ions.
13 . The sensor of claim 1 , wherein the MOS transistor comprises a third low-concentration diffusion region having a conductivity type opposite to the substrate.
14 . The sensor of claim 13 , wherein the third low-concentration diffusion region has a shallower dopant concentration profile than the first low-concentration diffusion region.
15 . The sensor of claim 13 , wherein the MOS transistor comprises a high-concentration diffusion region, at least partially overlapping with the third low-concentration diffusion region.
16 . The sensor of claim 15 , wherein the third low-concentration diffusion region has a shallower dopant concentration profile than the high-concentration diffusion region.
17 . The sensor of claim 1 , further comprising a high-concentration diffusion region.
18 . The sensor of claim 4 , further comprising a complementary low-concentration diffusion region on an upper surface of the photodiode which extends to the isolation layer and partially overlaps with the first low-concentration diffusion region.Join the waitlist — get patent alerts
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