US2010002112A1PendingUtilityA1

Cmos image sensor with noise cancellation

Assignee: CANDELA MICROSYSTEMS INCPriority: Nov 6, 2001Filed: Aug 4, 2009Published: Jan 7, 2010
Est. expiryNov 6, 2021(expired)· nominal 20-yr term from priority
Inventors:Hiok Nam Tay
H04N 25/616H04N 25/77H04N 25/771H04N 1/32358H04N 25/65H04N 25/70G11C 11/407H04N 1/40H04N 2201/3292H04N 9/642H04N 1/32491H04N 1/32475H04N 2201/0081H04N 25/78H10F 39/18
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Claims

Abstract

An image sensor having one or more pixels within a pixel array. A vertical signal line across the pixel array conductively connects to a drain terminal of a transistor of one of the pixels. The drain terminal is driven to a first drain voltage via the vertical signal line so that the transistor enters a triode region. A gate of the transistor is placed into a tri-state during the triode region, the gate being at a first gate voltage prior to the tri-state. The drain terminal is driven to a second drain voltage during the tri-state, whereby the gate is capacitively coupled to a second gate voltage. The second drain voltage may be higher than the first drain voltage so as to effectuate a gate voltage boosting for the transistor. The transistor may be a reset transistor having a drain terminal conductively coupled to reset said photodetector.

Claims

exact text as granted — not AI-modified
1 . A method for changing a gate voltage of a gate of a transistor in a pixel array of an image sensor, the transistor coupled to a photodetector in said pixel array, a vertical signal line across said pixel array coupled to transmit a voltage signal to a drain terminal of said transistor, comprising:
 driving said drain terminal to a first drain voltage via said vertical signal line so that said transistor enters a triode region;   placing said gate into a tri-state during said triode region, said gate being at a first gate voltage prior to said tri-state; and   driving said drain terminal to a second drain voltage during said tri-state, whereby said gate is capacitively coupled to a second gate voltage.   
     
     
         2 . The method of  claim 1 , wherein said second drain voltage is higher than said first drain voltage and said second gate voltage is higher than said first gate voltage. 
     
     
         3 . The method of  claim 1 , wherein said placing of said gate into a tri-state is by switching off a driving of a circuit, said circuit otherwise can output a current to said gate. 
     
     
         4 . The method of  claim 1 , wherein said transistor is a reset transistor and said drain terminal is conductively coupled to reset said photodetector. 
     
     
         5 . The method of  claim 1 , wherein said vertical signal line is an IN line. 
     
     
         6 . The method of  claim 1 , wherein said drain terminal is driven to said first drain voltage via a source terminal of said transistor. 
     
     
         7 . The method of  claim 2 , wherein a source terminal of said transistor has a voltage rise during said tri-state, whereby said gate is capacitively coupled from said source terminal. 
     
     
         8 . The method of  claim 2 , wherein a channel of said transistor has a voltage rise during said tri-state, whereby said gate is capacitively coupled from said channel. 
     
     
         9 . The method of  claim 1 , wherein said second drain voltage is a predetermined voltage.

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