Methods of Fabricating Nonvolatile Memory Devices

Abstract

Methods of fabricating nonvolatile memory devices are provided. An isolation layer is formed on a substrate. The substrate has a memory region and a well contact region and the isolation layer defines an active region of the substrate. A gate insulating layer is formed on the active region. The gate insulating layer is patterned to define an opening therein. The opening exposes at least a portion of the well contact region of the substrate and acts as a charge pathway for charges generated during a subsequent etch of the isolation layer. Related memory device are also provided.

1 . A method of fabricating nonvolatile memory device, the method comprising:
 forming an isolation layer on a substrate, the substrate having a memory region and a well contact region and the isolation layer defining an active region of the substrate;   forming a gate insulating layer on the active region; and   patterning the gate insulating layer to define an opening therein, the opening exposing at least a portion of the well contact region of the substrate; and   forming a first conductive layer on the gate insulating layer, the first conductive layer is self-aligned with the active region and is in contact with the well contact region through the opening.   
   
   
       2 . The method of  claim 1 , further comprising:
 selectively etching the isolation layer to expose at least a portion of a side surface of the first conductive layer.   
   
   
       3 . The method of  claim 2 , further comprising:
 forming a dielectric layer on the first conductive layer;   forming a second conductive layer on the dielectric layer; and   patterning the dielectric layer and the first and second conductive layers to provide stacked gate electrodes on the memory region and the well contact region of the substrate.   
   
   
       4 . The method of  claim 3 , wherein the opening is under the stacked gate electrode formed on the well contact region and electrically couples the first conductive layer and the substrate. 
   
   
       5 . The method of  claim 3 , wherein the opening is outside of the stacked gate electrode formed on the well contact region. 
   
   
       6 . The method of  claim 2 , wherein forming the gate insulating layer is followed by forming a buffer conductive layer on the gate insulating layer and wherein patterning further comprising patterning the buffer conductive layer to define the opening in the gate insulating layer and the buffer conductive pattern. 
   
   
       7 . The method of  claim 6 , wherein the selectively etching comprises:
 etching the isolation layer until a surface of the isolation layer is substantially planar with an upper surface of the first conductive layer; and then   etching the isolation layer until at least a portion of the side surface of the first conductive layer is exposed.   
   
   
       8 . The method of  claim 7 , wherein etching the isolation layer until the side surface of the first conductive layer is exposed comprises an anisotropic dry etching process. 
   
   
       9 . A method of fabricating a nonvolatile memory device, the method comprising:
 forming a gate insulating layer on a substrate, the substrate having a memory region and a well contact region;   patterning the gate insulating layer to define an opening therein, the opening exposing at least a portion of the well contact region of the substrate;   forming a first conductive layer on the gate insulating layer;   forming an isolation layer on the substrate, the isolation layer defining an active region; and   selectively etching the isolation layer to expose at least a portion of a side surface of the first conductive layer.   
   
   
       10 . The method of  claim 9 , further comprising:
 forming a dielectric layer on the first conductive layer;   forming a second conductive layer on the dielectric layer; and   patterning the dielectric layer and the first and second conductive layer to provide stacked gate electrodes on the memory region and the well contact region of the substrate.   
   
   
       11 . The method of  claim 10 , wherein the opening is under the stacked gate electrode formed on the well contact region and electrically couples the first conductive layer and the substrate. 
   
   
       12 . The method of  claim 10 , wherein the opening is outside of the stacked gate electrode formed on the well contact region. 
   
   
       13 . The method of  claim 9 , wherein the opening acts as a charge pathway for charges generated during a subsequent etch of the isolation layer.