US2009323427A1PendingUtilityA1

Semiconductor memory device

Assignee: PANASONIC CORPPriority: Apr 7, 2005Filed: Sep 8, 2009Published: Dec 31, 2009
Est. expiryApr 7, 2025(expired)· nominal 20-yr term from priority
Inventors:Toshio Mukunoki
G11C 16/0475G11C 29/74
41
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Claims

Abstract

A semiconductor memory device is provided which can achieve high performance, such as an improvement in reliability, an improvement in yield, and the like, without increasing the chip area. The semiconductor memory device is a non-volatile semiconductor memory device operable to program and erase data, and hold the data in the absence of a supplied voltage, comprising a memory cell including a first charge localized portion and a second charge localized portion each operable to store static charge corresponding to the data. The second charge localized portion stores static charge corresponding to static charge which should be stored in the first charge localized portion, thereby serving as a backup to the first charge localized portion.

Claims

exact text as granted — not AI-modified
1 - 15 . (canceled) 
   
   
       16 . The semiconductor memory device according to  claim 22 , comprising:
 a counter circuit for counting the number of times of reprogramming, and when the number of times of reprogramming counted exceeds a predetermined value, outputting a signal; and   a flag circuit for outputting a flag signal for changing the charge localized portions, based on the signal output from the counter circuit.   
   
   
       17 . The semiconductor memory device according to  claim 16 , wherein
 the counter circuit includes a plurality of memory sectors, including a predetermined number of memory cells, for counting different digits, and   when a carry occurs in a lower-digit memory sector, the counter circuit adds and programs one bit to an upper-digit memory sector and erase the lower-digit memory sector so as to count the number of times of reprogramming.   
   
   
       18 . The semiconductor memory device according to  claim 16 , wherein
 the counter circuit includes a plurality of memory cells, and counts the number of times of reprogramming by changing a threshold voltage Vt of the memory cell.   
   
   
       19 . The semiconductor memory device according to  claim 22 , comprising:
 a control circuit for outputting a signal when a predetermined phenomenon is detected during a program or erase operation; and   a flag circuit for outputting a flag signal for changing the charge localized portions, based on the signal output from the control circuit.   
   
   
       20 . The semiconductor memory device according to  claim 22 , wherein,
 when the first charge localized portion stores static charge, the second charge localized portion of the same memory cell stores static charge, and thereafter, the first charge localized portion is subjected to an erase operation before reading out data from the second charge localized portion.   
   
   
       21 . A non-volatile semiconductor memory device operable to program and erase data, and hold the data in the absence of a supplied voltage, comprising:
 a memory cell including a first charge localized portion and a second charge localized portion each capable of storing static charge corresponding to the data, wherein   the first charge localized portion is normally used to store static charge to store programmable and erasable data, and   when the first charge localized portion cannot normally store static charge, the second charge localized portion is used to store static charge storing data for specifying and repairing the first charge localized portion.   
   
   
       22 . A non-volatile semiconductor memory device operable to program and erase data, and hold the data in the absence of a supplied voltage, comprising:
 a memory cell including a first charge localized portion and a second charge localized portion each operable to store static charge corresponding to the data, and   a changing section for changing the charge localized portions which should store static charge corresponding to the data;   wherein the second charge localized portion stores static charge corresponding to static charge which should be stored in the first charge localized portion, thereby serving as a backup to the first charge localized portion, and   wherein when characteristics of the first charge localized portion are degraded due to actual use, the changing section changes the first charge localized portion to the second charge localized portion.

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