US2009321846A1PendingUtilityA1
Method of Forming Fully Silicided NMOS and PMOS Semiconductor Devices Having Independent Polysilicon Gate Thicknesses, and Related Device
Est. expiryApr 27, 2027(~0.7 yrs left)· nominal 20-yr term from priority
H10D 64/0132H10D 64/668H10D 64/017H10D 30/601H10D 30/0227H10D 84/0177H10D 84/0174H10D 84/038
50
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
A method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device. At least some of the illustrative embodiments are methods comprising forming an N-type gate over a semiconductor substrate (the N-type gate having a first thickness), forming a P-type gate over the semiconductor substrate (the P-type gate having a second thickness different than the first thickness), and performing a simultaneous silicidation of the N-type gate and the P-type gate.
Claims
exact text as granted — not AI-modified1 . A semiconductor device comprising:
a substrate comprising an N-type active area; an isolation structure abutting the N-type active area; a P-type active area abutting the isolation structure; an N-type gate on the N-type active area, the N-type gate having a first thickness; and a P-type gate on the P-type active area, the P-type gate having a second thickness different than the first thickness.
2 . The semiconductor device according to claim 1 wherein the first thickness is about 800 Angstroms and the second thickness is about 600 Angstroms.
3 . The semiconductor device according to claim 1 wherein the second thickness is about 75 percent of the first thickness.
4 . The semiconductor device according to claim 1 wherein the first thickness is greater than the second thickness by greater than about 20 Angstroms.Join the waitlist — get patent alerts
Track US2009321846A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.