System Having A Controller Device, A Buffer Device And A Plurality Of Memory Devices

Abstract

A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The second plurality of signal lines carries first address information from the integrated circuit buffer device to the first memory device. A third plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The third plurality of signal lines carries first control information from the integrated circuit buffer device to the first memory device. A first signal line is coupled to the first memory device and the integrated circuit buffer device. The first signal line carries a first signal from the integrated circuit buffer device to the first memory device. The first signal synchronizes communication of the first control information from the integrated circuit buffer device to the first memory device.

1 . (canceled) 
   
   
       2 . A memory system comprising:
 a substrate;   an integrated circuit master device incorporated on the substrate;   a first integrated circuit buffer device incorporated on the substrate;   a first point-to-point link coupled to the integrated circuit master device and the first integrated circuit buffer device, the first point-to-point link to transfer data, address, and control information between the integrated circuit master device and the first integrated circuit buffer device;   a first plurality of synchronous integrated circuit memory devices, coupled to the first integrated circuit buffer device, to store data received from the first integrated circuit buffer device;   a plurality of data lines coupled to the first integrated circuit buffer device and the first plurality of synchronous integrated circuit memory devices, the plurality of data lines to transport the data between the integrated circuit buffer device and the first plurality of synchronous integrated circuit memory devices; and   at least one signal line disposed alongside the plurality of data lines, the at least one signal line to convey a source synchronous signal that travels alongside data being transferred between the integrated circuit buffer device and at least a first synchronous integrated circuit memory device of the plurality of synchronous integrated circuit memory devices, such that the source synchronous signal is used to synchronize data transfer between the first synchronous integrated circuit memory device and the first integrated circuit buffer device.   
   
   
       3 . The memory system of  claim 2 , wherein the first plurality of synchronous integrated circuit memory devices is incorporated on the substrate. 
   
   
       4 . The memory system of  claim 2 , wherein the data, address and control information is transferred on the first point-to-point link using differential signals. 
   
   
       5 . The memory system of  claim 2 , wherein the data, address and control information is transferred as a plurality of packets. 
   
   
       6 . The memory system of  claim 5 , wherein the address and control information is transferred in a first packet of the plurality of packets. 
   
   
       7 . The memory system of  claim 2 , wherein the first plurality of synchronous integrated circuit memory devices are disposed on a memory module. 
   
   
       8 . The memory system of  claim 2 , wherein the source synchronous signal that travels alongside the data, travels edge aligned with the data. 
   
   
       9 . The memory system of  claim 2 , wherein the source synchronous signal is a clock signal. 
   
   
       10 . The memory system of  claim 2 , wherein the integrated circuit master device is a memory controller. 
   
   
       11 . The memory system of  claim 2 , further comprising:
 a second integrated circuit buffer device;   a second point-to-point link coupled to the integrated circuit master device and the second integrated circuit buffer device, the second point-to-point link to transfer data, address, and control information between the integrated circuit master device and the second integrated circuit buffer device; and   a second plurality of synchronous integrated circuit memory devices, coupled to the second integrated circuit buffer device, to store data received from the second integrated circuit buffer device.   
   
   
       12 . A memory system comprising:
 an integrated circuit master device;   a plurality of integrated circuit buffer devices;   a plurality of point-to-point links coupled to the integrated circuit master device and the plurality of integrated circuit buffer devices, the plurality of point-to-point links to transfer a plurality of packets between the integrated circuit master device and the plurality of integrated circuit buffer devices, wherein each packet of the plurality of packets includes write data and both address and control information associated with the write data; and   coupled to each integrated circuit buffer device of the plurality of integrated circuit buffer devices, a corresponding plurality of synchronous integrated circuit memory devices, wherein, for each integrated circuit buffer device, the corresponding plurality of integrated circuit memory devices stores the write data associated with both the address and the control information of the packet transferred over a point-to-point link coupled to the corresponding integrated circuit buffer device.   
   
   
       13 . The memory system of  claim 12 , wherein each point-to-point link of the plurality of point-to-point links includes:
 a first plurality of point-to-point signal lines to carry packets having write data, address and control information from the integrated circuit master device to a respective integrated circuit buffer device of the plurality of integrated circuit buffer devices; and   a second plurality of point-to-point signal lines to carry packets having read data from the respective integrated circuit buffer device to the integrated circuit master device.   
   
   
       14 . The memory system of  claim 13 , wherein the plurality of integrated circuit buffer devices includes a plurality of termination elements coupled to the first and second plurality of point-to-point signal lines. 
   
   
       15 . The memory system of  claim 12 , wherein the integrated circuit master device, the plurality of point-to-point links, the plurality of integrated circuit buffer devices, and the plurality of synchronous integrated circuit memory devices are disposed on a printed circuit board. 
   
   
       16 . The memory system of  claim 12 , wherein the integrated circuit master device and the plurality of point-to-point links are disposed on a first substrate and a first integrated circuit buffer device of the plurality of integrated circuit buffer devices, and the plurality of synchronous integrated circuit memory devices are disposed on a second substrate, wherein the first substrate is coupled to the second substrate via a connector. 
   
   
       17 . The memory system of  claim 12 , wherein each plurality of synchronous integrated circuit memory devices are memory devices that are incorporated on a memory module of a plurality of memory modules. 
   
   
       18 . The memory system of  claim 17 , wherein each memory module of the plurality of memory modules includes a corresponding integrated circuit buffer device of the plurality of integrated circuit buffer devices. 
   
   
       19 . A memory system comprising:
 an integrated circuit master device;   a plurality of point-to-point links coupled to the integrated circuit master device;   a plurality of repeater devices, each repeater device of the plurality of repeater devices coupled to a corresponding point-to-point link of the plurality of point-to-point links, wherein, via the plurality of point-to-point links, a plurality of packets is communicated between the integrated circuit master device and the plurality of repeater devices, wherein each packet of the plurality of packets includes write data and both address and control information associated with the write data; and   a plurality of memory modules coupled to the plurality of repeater devices, each memory module of the plurality of memory modules having a plurality of synchronous integrated circuit memory devices to receive write data, via each corresponding repeater device of the plurality of repeater devices, the write data provided from the integrated circuit master device to each repeater device via each corresponding point-to-point link of the plurality of point-to-point links.   
   
   
       20 . The memory system of  claim 19 , further including a plurality of integrated circuit buffer devices, each buffer device of the plurality of integrated circuit buffer devices to receive a packet from a corresponding point-to-point link and forward the write data to the plurality of synchronous integrated circuit memory devices for each module of the plurality of modules. 
   
   
       21 . The memory system of  claim 20 , wherein each buffer device of the plurality of integrated circuit buffer devices is disposed on a corresponding memory module of the plurality of memory modules. 
   
   
       22 . A memory system comprising:
 an integrated circuit master device;   a first integrated circuit buffer device;   a first point-to-point link coupled to the integrated circuit master device and the first integrated circuit buffer device, the first point-to-point link to transfer data, address, and control information between the integrated circuit master device and the first integrated circuit buffer device,   wherein the first point-to-point link includes,
 a first plurality of point-to-point signal lines to carry write data, address and control information from the integrated circuit master device to the first integrated circuit buffer device, and 
 a second plurality of point-to-point signal lines to carry read data from the first integrated circuit buffer device to the integrated circuit master device; and 
   a first memory module including a first plurality of synchronous integrated circuit memory devices to store data received from the first integrated circuit buffer device;   a second integrated circuit buffer device;   a second point-to-point link coupled to the integrated circuit master device and the second integrated circuit buffer device, the second point-to-point link to transfer data, address, and control information between the integrated circuit master device and the second integrated circuit buffer device,   wherein the second point-to-point link includes,
 a first plurality of point-to-point signal lines to carry write data, address and control information from the integrated circuit master device to the second integrated circuit buffer device, and 
 a second plurality of point-to-point signal lines to carry read data from the second integrated circuit buffer device to the integrated circuit master device; and 
   a second memory module including a second plurality of synchronous integrated circuit memory devices to store data received from the second integrated circuit buffer device.   
   
   
       23 . The memory system of  claim 22 , wherein the integrated circuit master device is a memory controller. 
   
   
       24 . The memory system of  claim 22 , wherein the integrated circuit master device is a central processing unit. 
   
   
       25 . The memory system of  claim 22 , wherein the data, address and control information is transferred as a plurality of packets. 
   
   
       26 . The memory system of  claim 22 , wherein the first memory module includes a first substrate having a first connector and the second memory module includes a second substrate having a second connector, wherein the integrated circuit master device is incorporated in a third substrate, wherein the first and second substrates are coupled to the third substrate via the first and second connectors. 
   
   
       27 . The memory system of  claim 22  wherein the integrated circuit master device and first and second integrated circuit buffers are incorporated on a first substrate.