Methods of Forming Integrated Circuit Devices Including Insulating Support Layers and Related Structures

Abstract

An integrated circuit device may include a substrate, a plurality of storage electrode landing pads on the substrate, and a plurality of storage electrodes. Each of the plurality of storage electrodes may be on a portion of a respective one of the plurality of storage electrode landing pads. In addition, an insulating support layer may be on the substrate, on portions of the storage electrode landing pads that are free of the storage electrodes, and on portions of sidewalls of storage electrodes. Moreover, portions of sidewalls of the storage electrodes may be free of the insulating support layer. Related methods and structures are also discussed.

1 . An integrated circuit device comprising:
 a substrate;   a plurality of storage electrode landing pads on the substrate;   a plurality of storage electrodes with each of the plurality of storage electrodes being on a portion of a respective one of the plurality of storage electrode landing pads;   an insulating support layer on the substrate, on portions of the storage electrode landing pads that are free of the storage electrodes, and on portions of sidewalls of storage electrodes, wherein portions of sidewalls of the storage electrodes are free of the insulating support layer: and   an active region of the substrate surrounded by isolation regions of the substrate, wherein a first one of the plurality of storage electrode landing pads is electrically coupled to a first end of the active region and a second one of the plurality of storage electrode landing pads is electrically coupled to a second end of the active region, and wherein the first one of the plurality of storage electrodes on the first storage electrode landing pad is offset relative to the active region.   
   
   
       2 . An integrated circuit device according to  claim 1  wherein a second one of the plurality of storage electrodes on the second storage electrode landing pad is aligned with the active region. 
   
   
       3 . An integrated circuit device comprising:
 a substrate including an active region surrounded by isolation regions;   a first storage electrode landing pad on the substrate wherein the first storage electrode landing pad is electrically coupled to a first end of the active region;   a second storage electrode landing pad on the substrate wherein the second storage electrode landing pad is electrically coupled to a second end of the active region;   a first storage electrode on a portion of the first storage electrode landing pad wherein the first storage electrode is offset relative to the active region; and   a second storage electrode on a portion of the second storage electrode landing pad.   
   
   
       4 . An integrated circuit device according to  claim 3  wherein the second storage electrode is aligned relative to the active region. 
   
   
       5 . An integrated circuit device according to  claim 3  further comprising:
 a bit line on the substrate wherein the bit line crosses the active region and wherein the first and second storage electrodes are on opposite sides of the bit line.   
   
   
       6 . An integrated circuit device according to  claim 5  further comprising:
 first and second word lines crossing the active region wherein the first and second wordlines cross the active region at a non-orthogonal angle.   
   
   
       7 . An integrated circuit device according to  claim 3  further comprising:
 an insulating support layer on the substrate, on portions of the storage electrode landing pads that are free of the storage electrodes, and on portions of sidewalls of storage electrodes, wherein portions of sidewalls of the storage electrodes are free of the insulating support layer.   
   
   
       8 . An integrated circuit device according to  claim 7  wherein each of the first and second storage electrode landing pads extends onto a portion of a sidewall of the respective first and second storage electrodes. 
   
   
       9 . An integrated circuit device according to  claim 3  wherein each of the first and second storage electrodes extends beyond an edge of the respective first and second storage electrode landing pads in a direction parallel to a surface of the substrate. 
   
   
       10 . An integrated circuit device according to  claim 3  further comprising:
 a capacitor dielectric layer on portions of the first and second storage electrodes; and   a plate electrode on the capacitor dielectric layer so that the capacitor dielectric layer is between the plate electrode and the first and second storage electrodes.   
   
   
       11 .- 18 . (canceled) 
   
   
       19 . An integrated circuit device comprising:
 a substrate;   a plurality of storage electrode landing pads on the substrate;   a plurality of storage electrodes with each of the plurality of storage electrodes being on a portion of a respective one of the plurality of storage electrode landing pads;   an insulating support layer on the substrate, on portions of the storage electrode landing pads that are free of the storage electrodes, and on portions of sidewalls of storage electrodes, wherein portions of sidewalls of the storage electrodes are free of the insulating support layer;   first and second adjacent bit lines on the substrate wherein the first and second adjacent bit lines are parallel, wherein the plurality of storage electrode landing pads include first and second adjacent storage electrode landing pads between the first and second adjacent bit lines, wherein a first one of the plurality of storage electrodes is on an end of the first storage electrode landing pad adjacent the first bit line, and wherein a second one of the plurality of storage electrodes is on an end of the second storage electrode landing pad adjacent the second bit line;   a first active region of the substrate electrically coupled to the first storage electrode landing pad;   a second active region of the substrate electrically coupled to the second storage electrode landing pad, wherein the first and second active regions are separated by isolation regions of the substrate; and   a word line on the substrate wherein the wordline is orthogonal with respect to the first and second bit lines and wherein the wordline crosses the first and second active regions;   wherein the first and second storage electrodes are respectively offset relative to portions of the first and second active regions.   
   
   
       20 . An integrated circuit device comprising:
 a substrate;   first and second bit lines on the substrate wherein the first and second adjacent bit lines are parallel;   first and second storage electrode landing pads on the substrate wherein the first and second storage electrode landing pads are between the first and second bit lines;   first and second storage electrodes respectively on a portions of the first and second storage electrode landing pads, wherein the first storage electrode is on an end of the first storage electrode landing pad adjacent the first bit line, and wherein the second storage electrode is on an end of the second storage electrode landing pad adjacent the second bit line;   a first active region of the substrate electrically coupled to the first storage electrode landing pad;   a second active region of the substrate electrically coupled to the second storage electrode landing pad, wherein the first and second active regions are separated by isolation regions of the substrate; and   a word line on the substrate wherein the wordline is orthogonal with respect to the first and second bit lines and wherein the wordline crosses the first and second active regions;   wherein the first and second storage electrodes are respectively offset relative to portions of the first and second active regions.