Electro-optic displays, and components for use therein

Abstract

An electro-optic display comprises a substrate ( 100 ), non-linear devices ( 102 ) disposed substantially in one plane on the substrate ( 100 ), pixel electrodes ( 106 ) connected to the non-linear devices ( 102 ), an electro-optic medium ( 110 ) and a common electrode ( 112 ) on the opposed side of the electro-optic medium ( 110 ) from the pixel electrodes ( 106 ). The moduli of the various parts of the display are arranged so that, when the display is curved, the neutral axis or neutral plane lies substantially in the plane of the non-linear devices ( 102 ).

1 . A field effect transistor comprising:
 a semiconductor layer;   source and drain electrodes in electrical contact with the semiconductor layer but spaced from one another so as to leave a channel region of the semiconductor layer therebetween;   a gate dielectric layer superposed on the channel region of the semiconductor layer; and   a gate electrode disposed on the opposed side of the gate dielectric layer from the channel region, such that variation of the voltage applied to the gate electrode can vary the conductivity of the channel region of the semiconductor layer, thus switching the transistor,   the gate dielectric layer extending over at least portions of the source and drain electrodes adjacent the channel region, an auxiliary dielectric layer being provided between the overlapping portions of the gate dielectric layer and the source and drain electrodes, the auxiliary dielectric layer not being present in at least part of the channel region.   
   
   
       2 . A field effect transistor according to  claim 1  wherein the auxiliary dielectric layer has a thickness at least twice as great as that of the gate dielectric layer. 
   
   
       3 . A field effect transistor according to  claim 1  wherein the auxiliary dielectric layer is formed from a low k dielectric having a k value not greater than about 3. 
   
   
       4 . A field effect transistor according to  claim 1  wherein the auxiliary dielectric layer is formed from silicon dioxide, a polyimide or a screen printable dielectric. 
   
   
       5 . A field effect transistor according to  claim 1  wherein the gate electrode is formed by printing. 
   
   
       6 . A field effect transistor array comprising at least two field effect transistors according to  claim 1  disposed adjacent one another, wherein the gate dielectric is continuous from one transistor to the other. 
   
   
       7 . A process for forming a field effect transistor, the process comprising:
 forming a layer of semiconductor material;   forming a layer of a conductive material superposed on the layer of semiconductor material;   forming an auxiliary dielectric layer superposed on the layer of conductive material;   patterning the auxiliary dielectric layer and the layer of conductive material, thereby forming from the layer of conductive material spaced source and drain electrodes separated by a channel region of the layer of semiconductor material, such that the auxiliary dielectric layer is removed from at least part of the channel region;   forming a gate dielectric layer overlying at least the channel region and adjacent portions of the source and drain electrodes; and   forming a gate electrode superposed on the gate dielectric layer and adjacent the channel region of the semiconductor layer.   
   
   
       8 . A process according to  claim 7  wherein the gate electrode is formed by printing. 
   
   
       9 . A process according to  claim 7  wherein the auxiliary dielectric layer has a thickness at least twice as great as that of the gate dielectric layer. 
   
   
       10 . A process for producing a transistor, the process comprising:
 forming a thin semiconductor layer;   printing spaced source and drain electrodes directly on to the semiconductor layer leaving a channel region of the semiconductor layer between the source and drain electrodes;   providing a gate dielectric layer superposed on the channel region of the semiconductor layer; and   providing a gate electrode on the opposed side of the gate dielectric layer from the channel region of the semiconductor layer.   
   
   
       11 . A process according to  claim 10  wherein the semiconductor layer has a thickness not greater than about 50 nm. 
   
   
       12 . A process according to  claim 10  wherein the semiconductor layer is formed of silicon. 
   
   
       13 . A backplane for an electro-optic display, the backplane comprising a plurality of pixel electrodes, and a ring diode associated with each pixel electrode, each ring diode comprising at least one organic layer. 
   
   
       14 . A backplane according to  claim 13  further comprising at least one column electrode in electrical contact with a plurality of the ring diodes, the column electrode being narrower than the layer of each ring diode in immediate contact with the column electrode. 
   
   
       15 . An electro-optic display comprising a backplane according to  claim 13  and a layer of electro-optic medium disposed adjacent the backplane such that by varying the voltages on the pixel electrodes, the optical state of the electro-optic medium can be varied, the electro-optic medium having a threshold for switching. 
   
   
       16 . A backplane for an electro-optic display, the backplane comprising a plurality of pixel electrodes, a diode associated with each pixel electrode, and at least one column electrode in electrical contact with a plurality of the diodes, the column electrode being narrower than the layer of each diode in immediate contact therewith. 
   
   
       17 . A backplane according to  claim 16  wherein the layer of each diode in immediate contact with the column electrode is organic. 
   
   
       18 . A backplane according to  claim 16  wherein at least one diode is a metal-insulator-metal diode. 
   
   
       19 . An electro-optic display comprising a backplane according to  claim 16  and a layer of electro-optic medium disposed adjacent the backplane such that by varying the voltages on the pixel electrodes, the optical state of the electro-optic medium can be varied, the electro-optic medium having a threshold for switching. 
   
   
       20 . A backplane for an electro-optic display, the backplane comprising a column electrode, a dielectric or semiconductor layer superposed on the column electrode, an upper dielectric layer superposed on the dielectric or semiconductor layer, and a pixel electrode superposed on the upper dielectric layer, the pixel electrode extending through an aperture in the upper dielectric layer and contacting the dielectric or semiconductor layer, wherein the width of the area of contact between the pixel electrode and the dielectric or semiconductor layer is not greater than about one-fourth of the width of the column electrode. 
   
   
       21 . A process for producing a plurality of non-linear devices on a substrate, the process comprising:
 forming an unpatterned layer of semiconductor material on the substrate;   forming at least two discrete areas of metal overlying the unpatterned semiconductor layer; and   etching the semiconductor layer using the discrete areas of metal as a mask, thereby patterning the layer of semiconductor material to leave at least two discrete areas of semiconductor material underlying the at least two discrete areas of metal.   
   
   
       22 . A process according to  claim 1  wherein the at least two discrete areas of metal are formed by depositing an unpatterned layer of metal over the semiconductor and thereafter patterning the layer of metal to form the at least two discrete areas of metal.