Top layers of metal for high performance IC's

Abstract

The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.

1 . A semiconductor chip comprising:
 a silicon substrate;   a transistor in or on said silicon substrate;   a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;   a dielectric layer between said first and second metal layers;   a contact pad over said silicon substrate, wherein said contact pad has a top surface with a first region, a second region and a third region between said first and second regions;   a passivation layer over said metallization structure, over said dielectric layer and on said first and second regions, wherein a first opening in said passivation layer is over said third region, and said third region is at a bottom of said first opening, and wherein said passivation layer comprises a nitride;   a first polymer layer on a fourth region of a top surface of said passivation layer, wherein a second opening in said first polymer layer is over said third region and over a fifth region of said top surface of said passivation layer, and wherein said first polymer layer has a thickness between 2 and 50 micrometers, greater than that of said dielectric layer and greater than that of said passivation layer;   a third metal layer on said first polymer layer, on said third and fifth regions and in said first and second openings, wherein said third metal layer is connected to said third region through said first and second openings, and wherein said third metal layer comprises a titanium-containing layer on said first polymer layer, on said third and fifth regions and in said first and second openings, a gold seed layer on said titanium-containing layer, and an electroplated gold layer with a thickness between 2 and 100 micrometers directly on said gold seed layer; and   a second polymer layer on said third metal layer and on said first polymer layer.   
   
   
       2 . The semiconductor chip of  claim 1 , wherein said titanium-containing layer comprises a titanium-tungsten-alloy layer on said first polymer layer, on said third and fifth regions and in said first and second openings. 
   
   
       3 . The semiconductor chip of  claim 1 , wherein said titanium-containing layer comprises a titanium-nitride layer on said first polymer layer, on said third and fifth regions and in said first and second openings. 
   
   
       4 . The semiconductor chip of  claim 1 , wherein said titanium-containing layer has a thickness between 0.01 and 3 micrometers. 
   
   
       5 . The semiconductor chip of  claim 1 , wherein said gold seed layer has a thickness between 0.05 and 3 micrometers. 
   
   
       6 . The semiconductor chip of  claim 1 , wherein said passivation layer further comprises an oxide. 
   
   
       7 . A semiconductor chip comprising:
 a silicon substrate;   a transistor in or on said silicon substrate;   a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;   a dielectric layer between said first and second metal layers;   a contact pad over said silicon substrate, wherein said contact pad has a top surface with a first region, a second region and a third region between said first and second regions;   a passivation layer over said metallization structure, over said dielectric layer and on said first and second regions, wherein a first opening in said passivation layer is over said third region, and said third region is at a bottom of said first opening, and wherein said passivation layer comprises a nitride;   a first polymer layer on a fourth region of a top surface of said passivation layer, wherein a second opening in said first polymer layer is over said third region and over a fifth region of said top surface of said passivation layer, and wherein said first polymer layer has a thickness between 2 and 50 micrometers, greater than that of said dielectric layer and greater than that of said passivation layer;   a third metal layer on said first polymer layer, on said third and fifth regions and in said first and second openings, wherein said third metal layer is connected to said third region through said first and second openings, and wherein said third metal layer comprises an adhesion layer on said first polymer layer, on said third and fifth regions and in said first and second openings, a copper seed layer over said adhesion layer, and an electroplated copper layer with a thickness between 2 and 100 micrometers directly on said copper seed layer; and   a second polymer layer on said third metal layer and on said first polymer layer.   
   
   
       8 . The semiconductor chip of  claim 7 , wherein said adhesion layer comprises a titanium layer on said first polymer layer, on said third and fifth regions and in said first and second openings. 
   
   
       9 . The semiconductor chip of  claim 7 , wherein said adhesion layer comprises a titanium-tungsten-alloy layer on said first polymer layer, on said third and fifth regions and in said first and second openings. 
   
   
       10 . The semiconductor chip of  claim 7 , wherein said adhesion layer comprises a titanium-nitride layer on said first polymer layer, on said third and fifth regions and in said first and second openings. 
   
   
       11 . The semiconductor chip of  claim 7 , wherein said third metal layer further comprises a nickel layer over said electroplated copper layer. 
   
   
       12 . The semiconductor chip of  claim 7 , wherein said first polymer layer comprises polyimide. 
   
   
       13 . The semiconductor chip of  claim 7 , wherein said copper seed layer has a thickness between 0.05 and 3 micrometers. 
   
   
       14 . The semiconductor chip of  claim 7 , wherein said passivation layer further comprises an oxide. 
   
   
       15 . A semiconductor chip comprising:
 a silicon substrate;   a transistor in or on said silicon substrate;   a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;   a dielectric layer between said first and second metal layers;   a contact pad over said silicon substrate, wherein said contact pad has a top surface with a first region, a second region and a third region between said first and second regions;   a passivation layer over said metallization structure, over said dielectric layer and on said first and second regions, wherein a first opening in said passivation layer is over said third region, and said third region is at a bottom of said first opening, and wherein said passivation layer comprises a nitride;   a polymer layer on a fourth region of a top surface of said passivation layer, wherein a second opening in said polymer layer is over said third region and over a fifth region of said top surface of said passivation layer, and wherein said polymer layer has a thickness between 2 and 50 micrometers, greater than that of said dielectric layer and greater than that of said passivation layer; and   a third metal layer on said polymer layer, on said third and fifth regions and in said first and second openings, wherein said third metal layer is connected to said third region through said first and second openings, and wherein said third metal layer comprises an adhesion layer on said polymer layer, on said third and fifth regions and in said first and second openings, a copper layer over said adhesion layer, and a nickel layer over said copper layer.   
   
   
       16 . The semiconductor chip of  claim 15 , wherein said adhesion layer comprises a titanium layer on said polymer layer, on said third and fifth regions and in said first and second openings. 
   
   
       17 . The semiconductor chip of  claim 15 , wherein said adhesion layer comprises a titanium-tungsten-alloy layer on said polymer layer, on said third and fifth regions and in said first and second openings. 
   
   
       18 . The semiconductor chip of  claim 15 , wherein said adhesion layer comprises a titanium-nitride layer on said polymer layer, on said third and fifth regions and in said first and second openings. 
   
   
       19 . The semiconductor chip of  claim 15 , wherein said polymer layer comprises polyimide. 
   
   
       20 . The semiconductor chip of  claim 15 , wherein said passivation layer further comprises an oxide.