Strained-silicon cmos device and method

Abstract

The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to the device channel. The uniaxial strain can be produced in a biaxially strained substrate surface by strain inducing liners, strain inducing wells or a combination thereof. The uniaxial strain may be produced in a relaxed substrate by the combination of strain inducing wells and a strain inducing liner. The present invention also provides a means for increasing biaxial strain with strain inducing isolation regions. The present invention further provides CMOS devices in which the device regions of the CMOS substrate may be independently processed to provide uniaxially strained semiconducting surfaces in compression or tension.

1 . A method of providing a semiconducting structure comprising:
 providing a substrate having at least one strained semiconducting surface, said at least one strained semiconducting surface having an internal strain in a first direction and a second direction having equal magnitude, wherein said first direction is within a same plane and is perpendicular to said second direction;   producing at least one semiconducting device atop said at least one strained semiconducting surface, said at least one semiconducting device comprising a gate conductor atop a device channel portion of said semiconducting surface, said device channel separating source and drain regions; and   forming a strain inducing liner atop said at least one gate region, wherein said strain inducing liner produces a uniaxial strain in a direction parallel to said device channel in said at least one semiconducting surface, wherein said magnitude of strain in said first direction is different than said second direction.   
   
   
       2 . The method of  claim 1  wherein providing said substrate having said at least one strained semiconducting layer comprises providing a tensile strained epitaxially grown semiconducting layer overlying a SiGe layer, said SiGe layer having Ge present in a concentration ranging from about 5% to about 30%; and
 said strain inducing liner comprises oxides, nitrides, doped oxides, or combinations thereof deposited using chemical vapor deposition under conditions that produce a compressive stress or a tensile stress.   
   
   
       3 . The method of  claim 1  wherein providing said substrate having said at least one strained semiconducting layer comprises providing a compressively strained epitaxially grown semiconducting layer overlying a silicon doped with carbon layer, said silicon doped with carbon layer having carbon is present in a concentration ranging from about 0.5% to 6%; and
 said strain inducing liner comprises oxides, nitrides, doped oxides, or combinations thereof deposited using chemical vapor deposition under conditions that produce a compressive stress or a tensile stress.   
   
   
       4 . A method of providing a semiconducting structure comprising:
 providing a substrate having at least one strained semiconducting surface, said at least one strained semiconducting surface having an internal strain in a first direction and a second direction having equal magnitude, wherein said first direction is within a same plane and is perpendicular to said second direction;   producing at least one semiconducting device atop said at least one strained semiconducting surface, said at least one semiconducting device comprising a gate conductor atop a device channel portion of said semiconducting surface, said device channel separating source and drain regions; and   forming strain inducing wells adjacent said at least one gate region, wherein said strain inducing wells produces a uniaxial strain in said at least one strained semiconducting surface in a direction parallel to said device channel, wherein said magnitude of strain in said first direction is different than said second direction.   
   
   
       5 . The method of  claim 4  wherein forming said strain inducing wells comprises etching a surface of said strained grown semiconducting surface to provide a recess and epitaxially growing a silicon containing strain inducing material within said recess, wherein silicon doped with carbon in a concentration ranging from about 0.5% to 6% within said recess provides tensile strain inducing wells and silicon germanium wherein Ge present in a concentration ranging from about 5% to about 50% within said recess provides compressive strain inducing wells. 
   
   
       6 . The method of  claim 5  wherein forming said etching comprises an etch process including directional and non-directional etching, wherein said recess undercuts spacers adjacent said at least one gate region. 
   
   
       7 . A method of providing a semiconducting structure comprising:
 providing a relaxed substrate;   producing at least one semiconducting device atop said relaxed substrate, said at least one semiconducting device comprising a gate conductor atop a device channel portion of said semiconducting surface, said device channel separating source and drain regions;   forming strain inducing wells adjacent said device channel; and   forming a strain inducing liner atop said at least one gate region, wherein said strain inducing liner and said strain inducing wells provide a uniaxial strain in said device channel.   
   
   
       8 . A method of providing a semiconducting structure comprising:
 providing a substrate having a first device region and a second device region,   producing at least one semiconducting device atop a device channel portion of said substrate in said first device region and said second device region; and   producing a uniaxial strain in said first device region and second device, wherein said uniaxial strain is in a direction parallel to said device channel of said first device region and said second device region.   
   
   
       9 . The method of  claim 8  wherein said uniaxial strain in said first device region and said second device region is in tension or in compression, wherein said uniaxial strain in said first device region is the same or different from said second device region. 
   
   
       10 . The method of  claim 9  wherein producing a uniaxial strain in said first device region and said second device region further comprises:
 processing said first device region and said second device region to provide a combination of strain inducing structures comprising a first combination of a biaxially strained semiconducting surface underlying said at least one semiconducting device and a strain inducing liner atop said at least one semiconductor device, a second combination including said biaxially strained semiconducting surface underlying said at least one semiconducting device and a strain inducing well adjacent said at least one semiconducting device, a third combination including said biaxially strained semiconducting surface underlying said at least one semiconducting device, strain inducing liner atop said at least one semiconducting device, and strain inducing wells adjacent said at least one semiconducting device or a fourth combination including a relaxed substrate underlying said at least one semiconducting device, said strain inducing liner atop said at least one semiconducting device on a relaxed surface and said strain inducing wells adjacent said at least one semiconducting device, wherein said combination of strain inducing structures in said first device region are identical to or different from said combination of strain inducing structures in said second device region.   
   
   
       11 . The method of claim  38  wherein said uniaxial strain in said first device region is in tension and comprises at least one nFET and said second device region is in compression and comprises at least one pFET.