Terminated input buffer with offset cancellation circuit

Abstract

A system and method for compensation of offset voltage in a digital differential input buffer driven by a terminated transmission line. Offset compensation currents are injected at the output of the first stage of the input buffer, which has a higher impedance than the terminated transmission line at the input of the buffer. The compensation current is determined by a network of MOS transistors, which saves die space compared to resistors. A pair of voltage multiplexers provides for compensation currents to correct offsets of either polarity. Offset correction currents are determined anew each time the system is powered up, compensating for component aging. The offset correction can also be performed while the input buffer is operating, during periods when the input is quiescent, and/or by adjusting the offset correction according to the duty cycle of the detected input.

1 . A system for receiving digital data, the system comprising:
 (a) an input buffer including at least a first differential amplifier;   (b) a comparator, and   (c) a compensation mechanism separate from said comparator,   
     said compensation mechanism configured to provide a plurality of trial compensation currents, wherein respective differential outputs of said first differential amplifier are drivingly connected to corresponding inputs of said comparator, and wherein respective outputs of said compensation mechanism are also drivingly connected to corresponding said inputs of said comparator, said outputs of said compensation mechanism being operational to drive a corresponding compensation current of said plurality of trial compensation currents into said respective inputs of said comparator so as to substantially cancel an offset voltage of said differential amplifier, 
     and wherein said compensation mechanism is further configured to apply a trial compensation current of said plurality of trial compensation currents for determining said corresponding compensation current using feedback from said comparator. 
   
   
       2 . The system of  claim 1 , wherein said compensation mechanism includes a current-control network including:
 (i) at least one current-control subnetwork including at least one transistor, and   (ii) a switch in series with each said current-control subnetwork,   
     wherein each respective said series switch is operative independently to switch a current of a corresponding said current-control subnetwork. 
   
   
       3 . The system of  claim 2 , wherein a said current-control subnetwork includes at least one MOS transistor. 
   
   
       4 . The system of  claim 1  further comprising:
 (d) a second differential amplifier drivingly connected to said first differential amplifier.   
   
   
       5 . The system of  claim 1  further comprising:
 (d) a second differential amplifier driven by said first differential amplifier and drivingly connected to said comparator.   
   
   
       6 . The system of  claim 1  further comprising:
 (d) a low-pass filter, driven by an output of said comparator, and operative to produce an output signal proportional to a duty cycle of said comparator output,   
     and wherein said corresponding compensation current is adjusted so as to cause said duty cycle of said comparator to be substantially equal to a pre-determined duty cycle. 
   
   
       7 . A method for compensating offset voltage in a digital differential input having a differential amplifier, the method comprising the steps of:
 (a) providing a comparator having inputs driven by outputs of the differential amplifier;   (b) calibrating the differential input by injecting a sequence of trial compensation currents into said inputs of said comparator while monitoring a first output of said comparator, and   (c) upon detecting a change of state of said first output of said comparator, selecting compensation currents substantially equal to said trial compensation currents corresponding to said change of state, for injection into said inputs of said comparator so as to substantially compensate the offset of the differential input.   
   
   
       8 . The method of  claim 7  wherein step (b) is performed upon application of power to the digital differential input. 
   
   
       9 . The method of  claim 7 , wherein step (b) is performed upon detection of a quiescent input signal. 
   
   
       10 . The method of  claim 7 , further comprising the step of:
 (d) operating the digital differential input while injecting said selected compensation currents into said inputs of said comparator.   
   
   
       11 . The method of  claim 7 , wherein said sequence of trial compensation currents is monotonic. 
   
   
       12 . The method of  claim 7 , further comprising the steps of:
 (d) measuring a duty cycle of a second output of said comparator;   (e) comparing said measured duty cycle with a pre-determined target duty cycle, and   (f) adjusting said selected compensation currents according to said comparison.   
   
   
       13 . The system of  claim 1 , wherein said compensation mechanism is further configured for recalibration to compensate for changes is said offset voltage. 
   
   
       14 . The system of  claim 1 , wherein said compensation mechanism is further configured to perform said determining after application of power to the system. 
   
   
       15 . The system of  claim 1 , wherein said compensation mechanism is further configured to perform said determining at a quiescent period of a transmission.