Method and system for vertical dmos with slots

Abstract

A method for providing a high power, low resistance, high efficient vertical DMOS device is disclosed. The method comprises providing a semiconductor substrate with a source body structure thereon. The method further comprises providing a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing. Also disclosed is a method for integrating this vertical DMOS with CMOS, bipolar and BCD to provide an optimized small, efficient die using the buried power buss approach and these technologies.

1 . A vertical DMOS device comprising:
 a semiconductor substrate, the semiconductor substrate including a source/body structure thereon; and   a plurality of interconnects through the source/body structure, each of the plurality of interconnects comprising one slot provided in the semiconductor substrate and at least one metal within the slot.   
   
   
       2 . The vertical DMOS device of  claim 1  wherein the semiconductor substrate comprises:
 a substrate region; and a buried layer, or Boron Up Diffusion where required and   an epitaxial (EPI) layer over the substrate region, wherein the source/body structures are provided in the EPI layer.   
   
   
       3 . The vertical DMOS device of  claim 1  wherein the source/body structure is continuous. 
   
   
       4 . The vertical DMOS device of  claim 3  wherein the plurality of interconnects comprise any of a ground strap, metal sinker and a power buss. 
   
   
       5 . The vertical DMOS device of  claim 4  wherein the ground strap is designed as macros of metal busses. 
   
   
       6 . The vertical DMOS device of  claim 4  wherein the body is not tied to ground. 
   
   
       7 . The vertical DMOS device of  claim 4  wherein the channel is vertical. 
   
   
       8 . The vertical DMOS device of  claim 4  wherein the array comprises a tight packing density. 
   
   
       9 . The vertical DMOS device of  claim 4  wherein the channels are short because they are determined by the difference between the junctions of source/body structure and the body/epi when fully inverted.