Stress enhanced transistor devices and methods of making

Abstract

Stress enhanced transistor devices and methods of fabricating the same are provided. In one embodiment, a transistor device comprises: a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the recessed regions undercut the dielectric spacers to form undercut areas of the channel region; and epitaxial source and drain regions disposed in the recessed regions of the semiconductor substrate and extending laterally underneath the dielectric spacers into the undercut areas of the channel region.

1 . A transistor device comprising:
 a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the recessed regions undercut the dielectric spacers to form undercut areas of the channel region; and   epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate and extending laterally underneath the dielectric spacers into the undercut areas of the channel region.   
   
   
       2 . The transistor device of  claim 1 , wherein the transistor device is a PFET device and the epitaxially grown source and drain regions comprise silicon germanium. 
   
   
       3 . The transistor device of  claim 1 , wherein the transistor device is an NFET device and the epitaxially grown source and drain regions comprise silicon carbide. 
   
   
       4 . The transistor device of  claim 1 , further comprising an etch stop region in the semiconductor substrate underneath the epitaxially grown source and drain regions 
   
   
       5 . The transistor device of  claim 3 , wherein the etch stop region comprises a p-type species, an n-type species, or an electrically inactive species. 
   
   
       6 . The transistor device of  claim 4 , wherein the p-type species comprises boron, boron fluoride, or a combination comprising at least one of the foregoing species. 
   
   
       7 . The transistor device of  claim 4 , wherein the electrically inactive species comprises silicon, germanium, carbon, xenon, or a combination comprising at least one of the foregoing species. 
   
   
       8 . The transistor device of  claim 1 , wherein the sidewalls of the channel region are indented such that the channel region is substantially shaped as an hourglass. 
   
   
       9 . The transistor device of  claim 1 , wherein the sidewalls of the channel region are slanted such that the sidewalls extend outwardly from the surface of the channel region toward a recessed surface of the semiconductor substrate. 
   
   
       10 . A method of fabricating a transistor device, comprising:
 providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers;   anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate spaced apart by a channel region;   selectively etching exposed sidewalls of the channel region to undercut the dielectric spacers; and   epitaxially growing source and drain regions in the recessed regions of the semiconductor substrate such that the source and drain regions extend underneath the dielectric spacers.   
   
   
       11 . The method of  claim 10 , wherein said selectively etching the exposed sidewalls of the channel region comprises contacting the semiconductor substrate with a hydroxide etchant to make the sidewalls of the channel region substantially shaped as an hourglass, and wherein the epitaxially grown source and drain regions comprise silicon germanium when the transistor device is a PFET device or silicon carbide when the transistor device is a NFET device. 
   
   
       12 . The method of  claim 10 , further comprising forming etch stop regions in the semiconductor substrate beneath the surfaces of the recessed regions prior to said selectively etching exposed sidewalls of the channel region, wherein said forming the etch stop regions comprises:
 implanting a p-type species if the transistor device is a PFET or implanting an n-type species if the transistor device is a NFET; and   annealing the semiconductor substrate.   
   
   
       13 . The method of  claim 12 , wherein the p-type species comprises boron implanted at an energy of less than about 10 keV and a dosage of about 2×e 14  ions/cm 2  to about 2×e 15  ions/cm 2 , boron difluoride implanted at an energy of less than about 10 keV and a dosage of about 2×e 14  ions/cm 2  to about 1×e 15  ions/cm 2 , or a combination comprising at least one of the foregoing species. 
   
   
       14 . The method of  claim 10 , further comprising forming etch stop regions in the semiconductor substrate beneath the surfaces of the recessed regions prior to said selectively etching exposed sidewalls of the channel region, wherein said forming the etch stop regions comprises implanting an electrically inactive species. 
   
   
       15 . The method of  claim 14 , wherein the electrically inactive species comprises silicon, germanium, carbon, xenon, or a combination comprising at least one of the foregoing species. 
   
   
       16 . A method of fabricating a transistor device, comprising:
 providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers;   selectively etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate that undercut the dielectric spacers and define a channel region between the recessed regions comprising undercut areas; and   epitaxially growing source and drain regions in the recessed regions of the semiconductor substrate such that the source and drain regions extend underneath the dielectric spacers into the undercut areas of the channel region.   
   
   
       17 . The method of  claim 16 , wherein said selectively etching the exposed regions of the semiconductor substrate comprises contacting the semiconductor substrate with a hydroxide etchant to make the sidewalls of the channel region slanted such that the sidewalls extend outwardly from a surface of the channel region toward a recessed surface of the semiconductor substrate, and wherein the epitaxially grown source and drain regions comprise silicon germanium when the transistor device is a PFET or silicon carbide when the transistor device is a NFET. 
   
   
       18 . The method of  claim 16 , further comprising forming etch stop regions a spaced distance below a surface of the semiconductor substrate on opposite sides of the dielectric spacers prior to said selectively etching, wherein said forming the etch stop regions comprises:
 implanting a p-type species if the transistor device is a PFET or implanting an n-type species if the transistor device is a NFET; and   annealing the semiconductor substrate.   
   
   
       19 . The method of  claim 18 , wherein the p-type species comprises boron implanted at an energy of about 10 keV to about 100 keV and a dosage of about 2×e 14  ions/cm 2  to about 2×e 15  ions/cm 2 , boron difluoride implanted at an energy of about 10 keV to about 100 keV and a dosage of about 2×e 14  ions/cm 2  to about 1×e 15  ions/cm 2 , or a combination comprising at least one of the foregoing species. 
   
   
       20 . The method of  claim 16 , further comprising forming etch stop regions a spaced distance below a surface of the semiconductor substrate on opposite sides of the dielectric spacers prior to said selectively etching, wherein said forming the etch stop regions comprises implanting silicon, germanium, carbon, xenon, or a combination comprising at least one of the foregoing species.