Sense amplifier and data sensing method thereof

Abstract

A data sensing method for sensing storage data stored in a memory cell includes the steps of: biasing a sensing node and a reference node to a first voltage in response to a first control signal; discharging the sensing node and the reference node via the memory cell and a reference memory cell, respectively; enabling a latch circuit to amplify a voltage difference between the sensing node and the reference node.

1 . A sense amplifier for sensing data stored in a memory cell of a memory, the sense amplifier comprising:
 a sensing node;   a reference node;   a first bias circuit for biasing the sensing node to a first voltage in response to a first control signal;   a second bias circuit for biasing the reference node to the first voltage in response to the first control signal;   a first transmission circuit for discharging the sensing node via the memory cell;   a second transmission circuit for discharging the reference node via a reference memory cell; and   a latch circuit for amplifying a voltage difference between the sensing node and the reference node.   
   
   
       2 . The sense amplifier according to  claim 1 , further comprising:
 a third bias circuit, for biasing the sensing node to a second voltage in response to a third control signal; and   
   
   
       3 . a fourth bias circuit, for biasing the reference node to the second voltage in response to the third control signal. The sense amplifier according to  claim 2 , wherein the first, second and third control signals have enabled levels respectively in a first period, a second period and a third period, the third period being between the first and second periods, and the first, second and third periods do not overlap with one another. 
   
   
       4 . The sense amplifier according to  claim 2 , wherein the first and second transmission circuits respectively comprise:
 a first transistor having a first source/drain coupled to the sensing node, a second source/drain for receiving the cell current and a gate for receiving an enabled signal; and   a second transistor having a first source/drain coupled to the reference node, a second source/drain for receiving the reference current and a gate for receiving the enabled signal,   wherein the second voltage biases the first and second transistors to operate in saturation regions.   
   
   
       5 . The sense amplifier according to  claim 1 , further comprising:
 a first switch having a first terminal coupled to the sensing node, and a second terminal coupled to a first input terminal of the latch circuit, wherein the first switch is enabled in response to an enabled level of a fourth control signal to provide a sensing voltage on the sensing node to the latch circuit; and   a second switch having a first terminal coupled to the reference node, and a second terminal coupled to a second input terminal of the latch circuit, wherein the second switch is enabled in response to the enabled level of the fourth control signal to provide a reference voltage on the reference node to the latch circuit.   
   
   
       6 . The sense amplifier according to  claim 5 , wherein the first, second, third and fourth control signals have enabled levels respectively in a first period, a second period, a third period and a fourth period, the fourth period being after the second period, and the first, second, third and fourth periods do not overlap with one another. 
   
   
       7 . The sense amplifier according to  claim 1 , further comprising:
 a first capacitor having one terminal coupled to the sensing node and the other terminal for receiving a third voltage; and   a second capacitor having one terminal coupled to the reference node and the other terminal for receiving the third voltage.   
   
   
       8 . The sense amplifier according to  claim 1 , wherein the latch circuit comprises:
 a first inverter having a first input terminal, a first output terminal and a first power input terminal, wherein the first input terminal and the first output terminal are respectively coupled to the sensing node and the reference node;   a second inverter having a second input terminal, a second output terminal and a second power input terminal, wherein the second input terminal and the second output terminal are respectively coupled to the reference node and the sensing node; and   a first transistor having a first terminal for receiving a fourth voltage and a second terminal coupled to the first and second power input terminals, wherein the first transistor is enabled in response to a fifth control signal to provide the fourth voltage to enable the first and second inverters.   
   
   
       9 . The sense amplifier according to  claim 8 , wherein the first and second inverters further respectively have a third power input terminal and a fourth power input terminal, and the latch circuit further comprises:
 a second transistor having a first terminal for receiving a fifth voltage and a second terminal coupled to the third and fourth power input terminals, wherein the second transistor is enabled in response to a sixth control signal to provide the fifth voltage to enable the first and second inverters.   
   
   
       10 . A data sensing method for sensing storage data stored in a memory cell of a memory, the data sensing method comprising:
 biasing a sensing node and a reference node to a first voltage in response to a first control signal;   discharging the sensing node via the memory cell, and discharging the reference node via a reference memory cell; and   enabling a latch circuit to amplify a voltage difference between the sensing node and the reference node.   
   
   
       11 . The method according to  claim 10 , further comprising:
 providing a sensing voltage on the sensing node and a reference voltage on the reference node to the latch circuit through switches respectively.   
   
   
       12 . The method according to  claim 10 , further comprising:
 biasing the sensing node and the reference node to a second voltage in response to an enabled level of a second control signal.