Chip capacitor precursors, packaged semiconductors, and assembly method for converting the precursors to capacitors

Abstract

A capacitive precursor ( 100 ) and packaged semiconductor devices therefrom includes a substrate ( 105 ), a plurality of electrically conductive material layers ( 111 - 118 ) stacked on the substrate ( 105 ). The plurality of electrically conductive layers ( 111 - 118 ) provide first and second patterns ( 200 and 250 ). The first patterns ( 200 ) each include at least a first pair of overlaying areas free of the electrically conductive material, and the second patterns ( 250 ) each include at least a second pair of overlaying areas free of the electrically conductive material. The first pair of areas overlay areas of the second pattern having the electrically conductive material and the second pair of areas overlay areas of the first pattern having the electrically conductive material. A plurality of dielectric layers ( 101 - 107 ) are interposed between neighboring electrically conductive material layers ( 111 - 118 ) for electrical isolation. One or more capacitive precursors can be dropped onto or into a board and during assembly of a packaged semiconductor device and have electrically conducting layers associated with its respective plates connected together to form a capacitor during assembly using conventional assembly steps.

1 . A capacitive precursor, comprising:
 a substrate;   a plurality of electrically conductive material layers stacked on said substrate, said plurality of electrically conductive material layers comprising first and second patterns, wherein said first patterns each comprise at least a first pair of overlaying areas free of said electrically conductive material, and said second patterns each comprise at least a second pair of overlaying areas free of said electrically conductive material, wherein said first pair of areas overlay areas of said second pattern having said electrically conductive material and said second pair of areas overlay areas of said first pattern having said electrically conductive material, and   a plurality of dielectric layers including respective ones of said plurality of dielectric layers between neighboring ones of said plurality of electrically conductive material layers,   wherein said plurality of electrically conductive material layers are electrically isolated from one another by said dielectric layers.   
     
     
         2 . The capacitive precursor of  claim 1 , wherein said substrate comprises a polymer or a ceramic printed circuit board (PCB). 
     
     
         3 . The capacitive precursor of  claim 1 , wherein said substrate comprises silicon. 
     
     
         4 . The capacitive precursor of  claim 1 , wherein said electrically conductive material comprises at least one metal. 
     
     
         5 . The capacitive precursor of  claim 1 , wherein at least one of said plurality of dielectric layers comprise a material having a k≧50. 
     
     
         6 . The capacitive precursor of  claim 1 , wherein said first pair of areas and second pair of areas are between 0.05 mm to 0.5 mm. 
     
     
         7 . The capacitive precursor of  claim 1 , wherein said first and second patterns both further comprise at least one common overlaying area that is free of said electrically conductive material. 
     
     
         8 . The capacitive precursor of  claim 1 , comprising a plurality of said capacitive precursors on said substrate. 
     
     
         9 . The capacitive precursor of  claim 8 , wherein said first and second patterns both further comprise at least one common overlaying area that is free of said electrically conductive. 
     
     
         10 . A packaged semiconductor device, comprising:
 a first printed circuit board (PCB) substrate;   first electrically conductive interconnect material on said first substrate;   at least one integrated circuit die on said first substrate coupled to said first interconnect;   at least one chip capacitor on a surface of said first substrate or embedded within said first substrate, said chip capacitor comprising:   a second substrate;   a plurality of electrically conductive material layers stacked on said second substrate, said plurality of electrically conductive material layers comprising first and second patterns, wherein said first patterns each comprise at least a first pair of overlaying areas free of said electrically conductive material, and said second patterns each comprise at least a second pair of overlaying areas free of said electrically conductive material, wherein said first pair of areas overlay areas of said second pattern having said electrically conductive material and said second pair of areas overlay areas of said first pattern having said electrically conductive material;   a plurality of dielectric layers including respective ones of said plurality of dielectric layers between neighboring ones of said plurality of electrically conductive layers; and   at least a first pair of vias formed in said first pair of areas free of said electrically conductive material filled with a second electrically conductive material which provides an electrical contact between said plurality of electrically conductive material layers comprising said first pattern and said plurality of electrically conductive material layers comprising said second pattern to provide respective capacitor plates of said chip capacitor,   wherein said first electrically conductive material is coupled to contact regions of said interconnect material on said first electrically conductive material.   
     
     
         11 . The packaged semiconductor device of  claim 10 , wherein said integrated circuit die comprises a plurality of said integrated circuit die stacked on one another, whereby said packaged semiconductor device comprises a system in package (SIP). 
     
     
         12 . The packaged semiconductor device of  claim 10 , wherein said integrated circuit die comprises a plurality of said integrated circuit die in a coplanar arrangement on a surface of said first substrate, whereby said packaged semiconductor device comprises a multi-chip module (MCM). 
     
     
         13 . The packaged semiconductor device of  claim 10 , wherein said chip capacitor comprises a decoupling capacitor connected a power supply terminal of said integrated circuit die and a ground for said integrated circuit die. 
     
     
         14 . The packaged semiconductor device of  claim 10 , wherein said second substrate comprises a polymer or a ceramic printed circuit board (PCB). 
     
     
         15 . The packaged semiconductor device of  claim 10 , wherein said second substrate comprises silicon. 
     
     
         16 . The packaged semiconductor device  claim 10 , wherein at least one of said plurality of dielectric layers comprise a material having a k≧50. 
     
     
         17 . The packaged semiconductor device  claim 10 , wherein said chip capacitor is on said surface of said first substrate. 
     
     
         18 . The packaged semiconductor device  claim 10 , wherein said chip capacitor is embedded within said first substrate. 
     
     
         19 . The packaged semiconductor device of  claim 10 , wherein said first and second patterns both further comprise at least one common overlaying area that is free of said electrically conductive material, wherein said common overlaying area that is free of said electrically conductive material is filled with said first electrically conductive material and is operable to provide a through via connection between said first electrically conductive interconnect material on a top surface of said first substrate to a second electrically conductive interconnect material on a bottom surface of said first substrate. 
     
     
         20 . A method of assembling a packaged semiconductor device comprising a first board substrate, at least one integrated circuit die on said first substrate, and at least one chip capacitor die having first and second capacitor plates coupled to said integrated circuit die on or embedded within said first substrate, said first substrate having electrically conductive contact regions thereon, comprising:
 dropping a pre-formed capacitor precursor on a surface of said first substrate or within said first substrate;   dropping said integrated circuit die on either of said first substrate;   if said pre-formed capacitor precursor lacks at least a first pair of vias for providing an electrical contact between capacitor plates of said chip capacitor, following said dropping said pre-formed capacitor precursor, forming at least a first pair of vias in said pre-formed capacitor precursor; and   filling said first pair of vias with an electrically conductive material to form said chip capacitor, wherein said filling of said vias provides an electrical contact between said first and second capacitor plates of said chip capacitor and said electrically conductive contact regions on said first substrate.   
     
     
         21 . The method of  claim 20 , wherein said pre-formed capacitor precursor comprises:
 a second substrate;   a plurality of electrically conductive material layers stacked on said second substrate, said plurality of electrically conductive material layers comprising first and second patterns, wherein said first patterns each comprise at least a first pair of overlaying areas free of said electrically conductive material, and said second patterns each comprise at least a second pair of overlaying areas free of said electrically conductive material, wherein said first pair of areas overlay areas of said second pattern having said electrically conductive material and said second pair of areas overlay areas of said first pattern having said electrically conductive material;   a plurality of dielectric layers including respective ones of said plurality of dielectric layers between neighboring ones of said plurality of metal layers; and   wherein said plurality of electrically conductive material layers are electrically isolated from one another by said dielectric layers.   
     
     
         22 . The method of  claim 21 , wherein said second substrate comprises a printed circuit board (PCB) substrate having a plurality of laminate layers, wherein said method includes said forming step, said forming step comprising drilling. 
     
     
         23 . The method of  claim 22 , wherein an entire one of said at least one of said plurality of laminate layers for said PCB is provided by said pre-formed capacitor precursor. 
     
     
         24 . The method of  claim 20 , wherein said pre-formed capacitor precursor comprises at least one pre-formed capacitor precursor die. 
     
     
         25 . The method of  claim 20 , wherein said second substrate comprises a printed circuit board (PCB) substrate having a plurality of laminate layers, and said pre-formed capacitor precursor die is embedded in at least one of said plurality of laminate layers. 
     
     
         26 . The method of  claim 21 , wherein said second substrate comprises an integrated circuit substrate. 
     
     
         27 . The method of  claim 26 , wherein said integrated circuit substrate comprises silicon. 
     
     
         28 . The method of  claim 21 , wherein at least one of said plurality of dielectric layers comprise a material having a k≧50. 
     
     
         29 . The method of  claim 20 , wherein said forming said vias comprises drilling. 
     
     
         30 . The method of  claim 29 , wherein said drilling is guided at least in part by stored position data for said packaged semiconductor device. 
     
     
         31 . The method of  claim 29 , wherein said drilling is guided at least in part by an on observable surface feature.