Fully differential dc offset device circuit

Abstract

A fully differential DC offset device circuit utilized in a high-pass filter is provided. The fully differential DC offset device circuit includes a first amplifying circuit, a second amplifying circuit and a Miller capacitor. The first amplifying circuit includes a first transistor and a second transistor, wherein a base of the first transistor is electrically connected to a base of the second transistor. The second amplifying circuit includes a third transistor and a fourth transistor, wherein a base of the third transistor is electrically connected to a base of the fourth transistor. The Miller capacitor includes an amplifier, wherein a first input terminal of the amplifier is electrically connected to the base of the second transistor of the first amplifying circuit, and a second input terminal of the amplifier is electrically connected to the base of the third transistor of the second amplifying circuit.

1 . A fully differential DC offset device circuit utilized in a high-pass filter, comprising:
 a first amplifying circuit having a first transistor and a second transistor, wherein the base of said first transistor is electrically connected to the base of said second transistor;   a second amplifying circuit having a third transistor and a fourth transistor, wherein the base of said third transistor is electrically connected to the base of said fourth transistor; and   a Miller capacitor having a amplifier, wherein a first input terminal of said amplifier is electrically connected to the base of said second transistor of said first amplifying circuit, and a second input terminal of said amplifier is electrically connected to the base of said third transistor of said second amplifying circuit.   
   
   
       2 . The fully differential DC offset device circuit as claimed in  claim 1 , wherein the base of said first transistor of said first amplifying circuit is electrically connected to a first terminal of a first resistor, and said second transistor is electrically connected to a second terminal of said first resistor. 
   
   
       3 . The fully differential DC offset device circuit as claimed in  claim 1 , wherein the base of said third transistor of said second amplifying circuit is electrically connected to a first terminal of a second resistor, and said fourth transistor is electrically connected to a second terminal of said second resistor. 
   
   
       4 . The fully differential DC offset device circuit as claimed in  claim 1 , wherein said first amplifying circuit further comprises a fifth transistor and a sixth transistor, the emitter of said fifth transistor is electrically connected to a first terminal of a third resistor, and the emitter of said sixth transistor is electrically connected to a second terminal of said third resistor. 
   
   
       5 . The fully differential DC offset device circuit as claimed in  claim 1 , wherein said second amplifying circuit further comprises a seventh transistor and a eighth transistor, the emitter of said seventh transistor is electrically connected to a first terminal of a fourth resistor, and the emitter of said eighth transistor is electrically connected to a second terminal of said fourth resistor. 
   
   
       6 . The fully differential DC offset device circuit as claimed in  claim 1 , wherein a first amplifying circuit further comprises a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor, and bases of said ninth transistor, said tenth transistor, said eleventh transistor and said twelfth transistor are electrically connected to each other. 
   
   
       7 . The fully differential DC offset device circuit as claimed in  claim 1 , wherein a second amplifying circuit further comprises a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor, and bases of said thirteenth transistor, said fourteenth transistor, said fifteenth transistor and said sixteenth transistor are connected to each other. 
   
   
       8 . The fully differential DC offset device circuit as claimed in  claim 1 , wherein said Miller capacitor further comprises a first capacitor and a second capacitor, said first capacitor electrically connects between said first input terminal and a first output terminal of said amplifier of said Miller capacitor, and said second capacitor electrically connects between said second input terminal and a second output terminal of said amplifier.