Contrast Interposer Stacking System And Method

Abstract

The present description provides increased contrast between interposer and leads in a stack embodiment that employs an interposer that extends beyond a boundary or perimeter established by the leads of the constituent IC devices.

1 . A circuit module comprised of:
 first and second leaded packaged integrated circuits in stacked disposition with the first leaded package being disposed above the second leaded package, each of which first and second leaded packaged integrated circuits having a body emergent from which are leads that each have a shoulder and foot, the shoulders each having a head;   a first interposer for electrical connection between the first and second leaded packaged integrated circuits, the first interposer having a dark portion and a light portion delineable with an imaginary line K, with the light portion being more reflective of light than is the dark portion and the first interposer having an external section and an internal section disposed on different sides of a line L defined by termini of a plurality of the feet of the leads of the first leaded packaged integrated circuit, the external section of the first interposer being further from the first packaged integrated circuit than is the internal section, and imaginary line K being closer to the body of the second packaged integrated circuit than is line L.   
   
   
       2 . The circuit module of  claim 1  in which the dark portion of the first interposer is realized with a contrast layer. 
   
   
       3 . The circuit module of  claim 1  in which the dark portion of the first interposer is realized with colored PCB material. 
   
   
       4 . The circuit module of  claim 1  in which the dark portion of the first interposer is realized with dyed PCB material. 
   
   
       5 . The circuit module of  claim 1  in which the first and second leaded packaged integrated circuits are flash memory devices. 
   
   
       6 . The circuit module of  claim 1  further comprising:
 a second interposer for electrical connection between the first and second leaded packaged integrated circuits, the second interposer having a dark portion and a light portion delineable with an imaginary line K with the light portion being more reflective of light than is the dark portion and the second interposer having an external section and an internal section disposed on different sides of a line L defined by termini of a plurality of the feet of the leads of the first leaded packaged integrated circuit, the external section of the second interposer being further from the first packaged integrated circuit than is the internal section, and imaginary line K being closer to the body of the second packaged integrated circuit than is line L.   
   
   
       7 . The circuit module of  claim 1  in which a first trace extends onto the external section of the first interposer. 
   
   
       8 . The circuit module of  claim 1  in which the first trace connects two non-adjacent ones of upper or lower connective elements of the first interposer. 
   
   
       9 . The circuit module of  claim 6  in which thermally conductive adhesive is disposed between the first and second leaded packaged integrated circuits. 
   
   
       10 . A circuit module comprising:
 an upper integrated circuit and a lower integrated circuit, each integrated circuit having a body having an upper surface, a lower surface, and a periphery emergent from which are a plurality of leads each having a shoulder and a foot having a terminus;   two carrier structures, each disposed on a peripheral side of the module between selected feet of the upper integrated circuit and selected shoulders of the lower integrated circuit to distance the upper integrated circuit above the lower integrated circuit, each of the two carrier structures having an internal section and an external section delineated by an imaginary line L coincident with the termini of the feet of the upper integrated circuit and each of the two carrier structures having on their respective lower sides, a dark area and a light area, the delineation between which areas being disposed closer to the body of the lower integrated circuit than is imaginary line L.   
   
   
       11 . The circuit module of  claim 10  in which the integrated circuits are TSOP packaged memory circuits. 
   
   
       12 . The circuit module of  claim 10  in which the integrated circuits are flash memory circuits. 
   
   
       13 . The circuit module of  claim 10  in which the carrier structures are comprised of printed circuit board material. 
   
   
       14 . The circuit module of  claim 10  in which thermally conductive material resides in the space between the upper and lower integrated circuits. 
   
   
       15 . The circuit module of  claim 10  in which the space between the upper and lower integrated circuits is an air gap. 
   
   
       16 . The circuit module of  claim 10  in which the two carrier structures are etched printed circuit board patterned to connect a no-connect one of the leads of the lower integrated circuit with an active lead of the upper integrated circuit. 
   
   
       17 . A circuit module comprising:
 first and second leaded packaged integrated circuits stacked one above the other and each having a body with peripheral sides and leads emergent from at least one of the peripheral sides, the leads having feet each of which feet having a terminus;   an interposer disposed between the leads of the first leaded packaged integrated circuit and the leads of the second leaded packaged integrated circuit, the interposer having a first side and a second side and having upper and lower connective elements respectively disposed along the first and second substantially planar surfaces of the interposer, at least a first area of the second substantially planar surface of the interposer being dark relative to a second area of the second substantially planar surface of the interposer.   
   
   
       18 . The circuit module of  claim 17  in which the first area of the second substantially planar surface of the interposer is covered with a contrast layer. 
   
   
       19 . The circuit module of  claim 18  in which the contrast layer is a layer of ink. 
   
   
       20 . The circuit module of  claim 19  in which the contrast layer is a solder mask.