Semiconductor device having transistor and method of manufacturing the same

Abstract

One embodiment of inventive concepts exemplarily described herein may be generally characterized as a semiconductor device including an isolation region within a substrate. The isolation region may define an active region. The active region may include an edge portion that is adjacent to an interface of the isolation region and the active region and a center region that is surrounded by the edge portion. The semiconductor device may further include a gate electrode on the active region and the isolation region. The gate electrode may include a center gate portion overlapping a center portion of the active region, an edge gate portion overlapping the edge portion of the active region, and a first impurity region of a first conductivity type within the center gate portion and outside the edge portion. The semiconductor device may further include a gate insulating layer disposed between the active region and the gate electrode.

1 . A semiconductor device comprising:
 an isolation region within a substrate, the isolation region defining an active region, the active region including an edge portion that is adjacent to an interface of the isolation region and the active region and a center region that is surrounded by the edge portion;   a gate electrode on the active region and the isolation region, the gate electrode including a center gate portion overlapping a center portion of the active region, an edge gate portion overlapping the edge portion of the active region, a first impurity region of a first conductivity type formed within the center gate portion and a second impurity region of a second conductivity type formed within the edge gate portion, the second conductivity type being opposite to the first conductivity type; and   a gate insulating layer disposed between the active region and the gate electrode.   
   
   
       2 . The semiconductor device of  claim 1 , wherein the second impurity region formed within the edge gate portion surrounds the first impurity region. 
   
   
       3 . (canceled) 
   
   
       4 . (canceled) 
   
   
       5 . The semiconductor device of  claim 1 , further comprising:
 a source region and a drain region in the active region at opposing sides of the gate electrode,   wherein each of the source region and the drain region includes impurities of the first conductivity type.   
   
   
       6 . The semiconductor device of  claim 5 , wherein the edge gate portion includes a first edge portion and a second edge gate portion located at opposing sides of the center gate portion and extending to the isolation region. 
   
   
       7 . (canceled) 
   
   
       8 . (canceled) 
   
   
       9 . The semiconductor device of  claim 6 , wherein the second impurity region is formed within each of the first edge gate portion and the second edge gate portion. 
   
   
       10 . The semiconductor device of  claim 9 , wherein an impurity concentration in the first edge gate portion is different from an impurity concentration in the second edge gate portion. 
   
   
       11 . The semiconductor device of  claim 6 , wherein one of the first edge gate portion and the second edge gate portion is undoped and the other of the first edge gate portion and the second edge gate portion includes the second impurity region. 
   
   
       12 . The semiconductor device of  claim 1 , wherein the gate electrode comprises:
 a first pair of opposing side walls overlapping the isolation region; and   a second pair of opposing side walls overlapping the active region.   
   
   
       13 . The semiconductor device of  claim 12 , wherein the center gate portion is separated from the first pair of opposing side walls and the second pair of opposing side walls. 
   
   
       14 . The semiconductor device of  claim 13 , wherein the edge gate portion includes a first edge gate portion and a second edge gate portion, which respectively extend from the first pair of opposing side walls to the center gate portion. 
   
   
       15 . (canceled) 
   
   
       16 . (canceled) 
   
   
       17 . The semiconductor device of  claim 14 , a wherein the second impurity region is formed within each of the first edge gate portion and the second edge gate portion. 
   
   
       18 . The semiconductor device of  claim 17 , wherein an impurity concentration in the first edge gate portion is different from an impurity concentration in the second edge gate portion. 
   
   
       19 . The semiconductor device of  claim 14 , wherein one of the first edge gate portion and the second edge gate portion is undoped and the other of the first edge gate portion and the second edge gate portion includes a second impurity region of a second conductivity type opposite to the first conductivity type. 
   
   
       20 . The semiconductor device of  claim 1 , wherein the gate electrode includes polysilicon 
   
   
       21 - 32 . (canceled) 
   
   
       33 . A semiconductor device comprising:
 an isolation region within a substrate, the isolation region defining an active region, the active region including an edge portion that is adjacent to an interface of the isolation region and the active region, and a center region that is surrounded by the edge portion;   a gate electrode on the active region and the isolation region, the gate electrode including a center gate portion overlapping a center portion of the active region, an edge gate portion overlapping the edge portion of the active region, and a first impurity region of a first conductivity type formed only in the center gate portion;   a gate insulating layer disposed between the active region and the gate electrode;   a source region and a drain region in the active region at opposing sides of the gate electrode, wherein each of the source region and the drain region is disposed between the gate electrode and the isolation region; and   a source drift region and a drain drift region in the active region, wherein each of the source drift region and the drain drift region surrounds the source region and the drain region, respectively, and wherein each of the source drift region and the drain drift region has a bottom lower than a bottom of the isolation region and surrounds an edge of the bottom of the isolation region respectively.