Solver for hardware based computing

Abstract

Full-AC load flow constitutes a core computation in power system analysis. The present invention provides a performance gain with a hardware implementation of a sparse-linear solver using a Field Programmable Gate Array (FPGA). The invention also relates to the design, simulation, and hardware verification of a static transmission line model for analog power flow computation. Operational transconductance amplifiers are employed in the model based on a previously proposed DC emulation technique of power flow computation, and provide reconfigurability of transmission line parameters via transconductance gain. The invention also uses Analog Behavioral Models (ABMs) in an efficient strategy for designing analog emulation engines for large-scale power system computation. Results of PSpice simulations of these emulation circuits are compared with industrial grade numerical simulations for validation. The application is also concerned with the development of a generator model using analog circuits for load flow emulation for power system analysis to reduce computation time. The generator model includes reconfigurable parameters using operational transconductance amplifiers (OTAs). The circuit module is used with other reconfigurable circuits, i.e., transmission lines and loads.

1 . An apparatus for carrying out complex computations which comprises:
 a field programmable gate array, said field programmable gate array programmed for implementation of Gaussian elimination by decomposition of a matrix into lower and upper triangulation factors and forward and backward elimination;   memory operably connected to said field programmable gate array, and   a device for maintaining pivoting information operably connected to said field programmable gate array.   
     
     
         2 . Apparatus as claimed in  claim 1 , wherein said device for maintaining pivoting information comprises a lookup table and memory pointers. 
     
     
         3 . Apparatus as claimed in  claim 2 , wherein said field programmable gate array implements the following Gaussian elimination for each column in the matrix loop:
 (a) search the column for a pivot element;   (b) pivot if necessary;   (c) normalize a pivot column;   (d) update a remaining portion of the matrix;   (e) multiply to form a sub-matrix update; and   (f) update a value or create a fill-in.   
     
     
         4 . Apparatus as claimed in  claim 3 , wherein said apparatus is configured to simultaneously perform memory reads and memory writes between said field programmable gate array and said memory. 
     
     
         5 . Apparatus as claimed in  claim 4 , further comprising a random access memory for storing an array of the indices of non-zero elements in the matrix, said random access memory being operably connected to said field programmable gate array. 
     
     
         6 . Apparatus as claimed in  claim 5 , further comprising index rejection logic to select appropriate indices from said stored array of indices. 
     
     
         7 . Apparatus as claimed in  claim 6 , wherein said memory comprises a row cache of memory of sufficient size to store a largest sub-matrix update for said computation. 
     
     
         8 . Apparatus as claimed in  claim 7 , wherein further comprising a table to keep track of elimination progress. 
     
     
         9 . Apparatus as claimed in  claim 1 , wherein said complex computation involves solution of at least one sparse linear system. 
     
     
         10 . Apparatus as claimed in  claim 1 , configured to emulate power flow in a power transmission system. 
     
     
         11 . A method for carrying out complex computations which comprises the steps of:
 (a) implementing Gaussian elimination by decomposition of a matrix into lower and upper triangulation factors and forward and backward elimination;   (b) storing and retrieving matrix values in a memory; and   (c) maintaining pivoting information.   
     
     
         12 . A method as claimed in  claim 11 , wherein said step of implementing Gaussian elimination comprises the steps of:
 Gaussian elimination for each column in the matrix loop:   (a) searching a column of the matrix for a pivot element;   (b) pivoting, if necessary;   (c) normalizing a pivot column;   (d) updating a remaining portion of the matrix;   (e) multiplying to form a sub-matrix update; and   (f) updating a value or create a fill-in.   
     
     
         13 . A method as claimed in  claim 12 , wherein said step of storing and retrieving matrix values in memory comprises simultaneously storing and retrieving matrix values. 
     
     
         14 . A method as claimed in  claim 13 , further comprising the step of tracking elimination progress to track elements that have already been eliminated. 
     
     
         15 . A method as claimed in  claim 14 , further comprising the step of selecting indices from said stored array to avoid selection of matrix elements that have already been eliminated. 
     
     
         16 . A system for emulating power flow in a power transmission system, which comprises:
 a power supply;   a variable resistor including at least one reconfigurable operational transconductance amplifier operably connected to said power supply; and   a device for measuring a current or voltage output of said system.   
     
     
         17 . A system as claimed in  claim 16 , comprising at least two reconfigurable operational transconductance amplifiers for modeling power transmission in at least two directions. 
     
     
         18 . A method for emulating a power transmission system comprising the steps of:
 (a) calculating a complex voltage from at least one generator using a dynamic swing equation;   (b) calculating a complex current flowing in a branch of said power transmission system; and   (c) calculating a real power of said at least one generator; and   (d) updating the dynamic swing equation based on a result of step (c).   
     
     
         19 . A method as claimed in  claim 18 , further comprising the step of:
 (e) solving for a steady-state solution.   
     
     
         20 . A method as claimed in  claim 19 , further comprising the step of:
 (f) correcting for offset of said steady-state solution by calculating an offset solution for zero mechanical input power, and subtracting the offset solution from said steady-state solution.