Semiconductor device

Abstract

A semiconductor device includes a plurality of memory cell blocks, each including a plurality of memory cells each storing a predetermined amount of data. Each of the memory cell blocks stores, in the memory cells thereof, truth table data used for outputting desired logical values in response to input of a given address so as to function as a logic circuit. The number of inputs and the number of outputs of the memory cell block is three or more, and the memory cell blocks are connected to each other so that three or more outputs from one memory cell block are input to three or more other memory cell blocks.

1 . A semiconductor device comprising:
 a plurality of memory cell blocks, each including a plurality of memory cells each storing a predetermined amount of data;   wherein each of the memory cell blocks stores, in the memory cells thereof, truth table data used for outputting desired logical values in response to input of a given address so as to function as a logic circuit, and wherein the number of inputs and the number of outputs of the memory cell block is three or more, and the memory cell blocks are connected to each other so that three or more outputs from one memory cell block are input to three or more other memory cell blocks.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the number of inputs and the number of outputs of the memory cell block is four, and the memory cell blocks are connected to each other so that four outputs from one memory cell block are input to four other memory cell blocks. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the plurality of memory cell blocks have a rectangular shape of the same size, and wherein the memory cell blocks are connected to each other such that at least some of the memory cell blocks are positionally shifted from an array arrangement. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the plurality of memory cell blocks are arranged in an array and are connected to each other using interconnection lines. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein each of the memory cell blocks further includes two read address decoders therein, and the memory cell includes two read word lines corresponding to the two read address decoders, and wherein, when a voltage is applied to the two read word lines, data stored in the memory cell is read out using a read data line. 
     
     
         6 . The semiconductor device according to  claim 1 , further comprising:
 a write address decoder connected to the plurality of memory cell blocks, the write address decoder specifying an x address related to the plurality of memory cell blocks and the memory cell in the memory cell blocks; and   a write/read circuit connected to the plurality of memory cell block, the write/read circuit specifying a y address related to the plurality of memory cell blocks and the memory cell in the memory cell blocks so as to write data to the memory cell;   wherein the data is written to the memory cell by the write/read circuit when the memory cell is specified by the write address decoder and the write/read circuit.   
     
     
         7 . The semiconductor device according to  claim 1 , wherein the semiconductor device functions as a normal storage device when the memory cell of the memory cell block does not store the truth table data. 
     
     
         8 . The semiconductor device according to  claim 7 , wherein an operating area of the memory cell of the memory cell block is separated into two, and wherein, when a particular address select line of the read address decoder is switched, the operating areas of the memory cell are switched so that switching between an operation in which the memory cell functions as two logic circuits and an operation in which the memory cell functions as a logic circuit and a normal storage device is instantaneously performed. 
     
     
         9 . The semiconductor device according to  claim 1 , wherein, when truth table data stored in memory cells in some of the memory cell blocks is updated, the operation of the semiconductor device is changed in accordance with the updated truth table data. 
     
     
         10 . The semiconductor device according to  claim 1 , wherein the semiconductor device is included in a system LSI, the semiconductor device performs a self-test function, and the semiconductor device tests other logic circuits included in the system LSI. 
     
     
         11 . The semiconductor device according to  claim 1 , wherein the semiconductor device operates on the basis of a compilation result of a C language program that describes the operation of the semiconductor device.