Flash memory device and method of programming the same

Abstract

A flash memory device and a method of programming the same are disclosed. The flash memory device includes an array of memory cells intersected by a plurality of bit lines and a plurality of word lines. A page buffer circuit includes a plurality of latches coupled to an even virtual bit line and an odd virtual bitline. The page buffer circuit is configured to load data into the array of memory cells responsive to a select circuit, which is structured to electrically couple at least some of the bit lines to the plurality of latches of the page buffer circuit.

1 . A flash memory device comprising:
 an array of memory cells disposed on intersection regions of a plurality of bit lines and a plurality of word lines;   a select circuit to select a plurality of bit lines arranged adjacently; and   a page buffer circuit to program a plurality of adjacent memory cells in the same word line corresponding to the selected bit lines,   wherein Least Significant Bits (LSB) of the adjacent memory cells are simultaneously programmed, and Most Significant Bits (MSB) of the adjacent memory cells are simultaneously programmed.   
   
   
       2 . The flash memory device of  claim 1 , wherein the select circuit electrically couples a first bit line to a first latch of the page buffer circuit, and couples a second bit line to a second latch of the page buffer circuit. 
   
   
       3 . The flash memory device of  claim 2 , wherein the plurality of adjacent memory cells in the same word line associated with the first bit line and the second bit line are simultaneously programmed responsive to data stored in the first latch and the second latch. 
   
   
       4 . The flash memory device of  claim 1 , wherein the adjacent memory cells on the same word line have a same page address. 
   
   
       5 . The flash memory device of  claim 4 , wherein the LSB of the adjacent memory cells comprise a first page address, and wherein the MSB of the adjacent memory cells comprise a second page address. 
   
   
       6 . A flash memory device comprising:
 a memory array intersected by a plurality of bit lines;   a select circuit configured to electrically couple a first even bit line to a first latch, and to electrically couple a second bit line being adjacent to the first bit line to a second latch; and   a page buffer circuit to program a plurality of adjacent memory cells in a same word line associated with the first bit line and the second bit line responsive to data stored in the first latch and the second latch.   
   
   
       7 . The flash memory device of  claim 6 , wherein the adjacent memory cells in the same word line have a same page address. 
   
   
       8 . The method of  claim 6 , wherein a Least Significant Bit (LSB) of each of the adjacent memory cells are simultaneously programmed, and wherein a Most Significant Bit (MSB) of each of the adjacent memory cells are simultaneously programmed. 
   
   
       9 . The method of  claim 8 , wherein the LSB of each of the adjacent memory cells comprise a first page, and wherein the MSB of each of the adjacent memory cells comprise a second page. 
   
   
       10 . A method for programming a memory cell, comprising:
 selecting n adjacent memory cells coupled to n adjacent bit lines, each of the n adjacent memory cells having a Least Significant Bit (LSB) and a Most Significant Bit (MSB); and   simultaneously programming the selected n adjacent memory cells of a word line.   
   
   
       11 . The method of  claim 10 , wherein the n adjacent memory cells in the same word line have a same page address. 
   
   
       12 . The method of  claim 10 , wherein the LSB of each of the adjacent memory cells are simultaneously programmed, and wherein the MSB of each of the adjacent memory cells are simultaneously programmed. 
   
   
       13 . The method of  claim 12 , wherein the LSB of each of the adjacent memory cells comprise a first page, and wherein the MSB of each of the adjacent memory cells comprise a second page.