Ultra-thin soi cmos with raised epitaxial source and drain and embedded sige pfet extension

Abstract

A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs.

1 . A semiconductor transistor device comprising:
 a semiconductor substrate having a buried layer of insulator material formed therein and an Ultra-thin Silicon On Insulator (UTSOI) layer formed a top said buried layer of insulator material;   STI (Shallow Trench Isolation) structures formed in said UTSOI layer for isolating active areas for forming an NFET device and PFET for forming a gate channel region for respective NFET and PFET device;   a gate structure including a gate dielectric layer formed in each isolated active area for each respective NFET and PFET device and a gate electrode conductor formed atop each said respective gate dielectric layer for each respective NFET and PFET device;   epitaxially grown embedded semiconductor extensions formed in respective recesses created as a result of removing portions of the SOI layer at respective source region and drain region at each side of said gate electrode of said PFET device;   raised source/drain (RSD) structures on top of respective epitaxially grown embedded semiconductor extensions corresponding to said source and drain regions of the PFET device; and,   raised source/drain (RSD) structures on top of source and drain regions of the NFET device,   wherein said epitaxially grown embedded semiconductor extensions create compressive stress in the UTSOI layer thereby enhancing PFET device performance.   
   
   
       2 . The semiconductor transistor device as claimed in  claim 1 , wherein said formed eSiGe extensions abut the short SOI channel region to maximize its compressive stress effect. 
   
   
       3 . The semiconductor transistor device as claimed in  claim 1 , wherein said formed epitaxial raised source/drain (RSD) structures range between 100 to 400 angstroms in thickness for said PFET device. 
   
   
       4 . The semiconductor transistor device as claimed in  claim 1 , wherein, for each formed NFET and PFET device, each said formed epitaxial RSD structures are located a distance from an edge of a respective gate conductor that is sufficient to lower parasitic capacitance between the gate and the respective source/drain structure for each formed NFET and PFET device. 
   
   
       5 . The semiconductor transistor device as claimed in  claim 1 , wherein said distance between between each formed RSD structure and a respective gate edge is between 30 nm-40 nm. 
   
   
       6 . A semiconductor transistor device comprising:
 a semiconductor substrate having a buried layer of insulator material formed therein and an Ultra-thin Silicon On Insulator (UTSOI) layer formed a top said buried layer of insulator material, said UTSOI layer providing an active area for a PFET device;   a gate structure including a gate dielectric layer formed in said UTSOI active area for said PFET device and a gate electrode conductor formed atop said gate dielectric layer;   epitaxially grown embedded semiconductor extensions formed in respective recesses created as a result of removing portions of the UTSOI layer at respective source region and drain region at each side of said gate structure of said PFET device; and,   raised source/drain (RSD) structures on top of respective epitaxially grown embedded semiconductor extensions,   wherein said epitaxially grown embedded semiconductor PFET extensions create compressive stress in the UTSOI layer thereby enhancing PFET device performance.