CMOS Image Sensor and Method of Manufacturing the Same

Abstract

Disclosed herein are a CMOS image sensor and a method of manufacturing the same, which can reduce current leakage through a plug connecting a photodiode and a transfer transistor to each other, and thereby provide low dark current levels. The CMOS image sensor includes a first epitaxial layer on or in a substrate. A photodiode PD is in the first epitaxial layer. A second epitaxial layer is on or in the substrate (e.g., on the first epitaxial layer). A shallow trench isolation region is in an area of the substrate. A plug is in the substrate (e.g., the second epitaxial layer) connected with the photodiode and spaced apart from the shallow trench isolation region. A transfer transistor having a gate electrode and source/drain regions is connected with the plug.

1 . A CMOS image sensor having a photodiode and a transfer transistor, the image sensor comprising:
 a substrate comprising a first epitaxial layer and a second epitaxial layer on the first epitaxial layer;   a photodiode PD in the first epitaxial layer;   a shallow trench isolation region in the substrate;   a plug in the substrate connected with the photodiode and spaced apart from the shallow trench isolation region; and   a transfer transistor having a gate electrode and source/drain regions, connected with the plug.   
   
   
       2 . The image sensor as claimed in  claim 1 , wherein the transfer transistor further comprises:
 a gate insulation film under the gate electrode;   wherein the source/drain regions are in the substrate at opposite sides of the gate electrode.   
   
   
       3 . The image sensor as claimed in  claim 2 , wherein the source region of the transfer transistor is connected with the plug. 
   
   
       4 . The image sensor as claimed in  claim 1 , wherein the CMOS image sensor is a vertical CMOS image sensor. 
   
   
       5 . The image sensor as claimed in  claim 2 , wherein the transfer transistor further comprises a sidewall spacer on a side wall of the gate electrode. 
   
   
       6 . The image sensor as claimed in  claim 5 , wherein the transfer transistor further comprises a lightly doped drain (LDD) region in the substrate under the sidewall spacer. 
   
   
       7 . The image sensor as claimed in  claim 1 , wherein the plug is in the second epitaxial layer 
   
   
       8 . A CMOS image sensor, comprising:
 a substrate;   a photodiode PD in the substrate;   an epitaxial layer on the substrate;   a shallow trench isolation region in the epitaxial layer;   a plug in the epitaxial layer connected with the photodiode and spaced apart from the shallow trench isolation region; and   a transfer transistor having a gate electrode and source/drain regions, where the source region is connected with the plug.