US2009286354A1PendingUtilityA1
Semiconductor chip having gettering layer, and method for manufacturing the same
Est. expiryJul 28, 2024(expired)· nominal 20-yr term from priority
H10W 90/754H10W 90/734H10W 90/732H10W 90/231H10W 90/20H10W 72/5522H10W 72/5363H10W 72/884H10W 72/536H10W 90/00
51
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Claims
Abstract
In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 μm or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.
Claims
exact text as granted — not AI-modified1 . A method for manufacturing a semiconductor package, comprising:
forming an element layer on a front face of a semiconductor wafer, the element layer including a transistor; dicing the semiconductor wafer so as to form a first semiconductor chip, after forming the element layer; polishing a back face of the first semiconductor chip so as to form a getting layer on the back face, after dicing the semiconductor wafer; and assembling a semiconductor package which includes a package substrate, a second semiconductor chip formed over the package substrate, the first semiconductor chip being formed over the second semiconductor chip, after polishing the back face of the first semiconductor chip, wherein the semiconductor package includes the gettering layer, the gettering layer is a damaged layer; the damaged layer includes a plurality of grooves, a thickness of the first semiconductor chip is thinner than a thickness of the second semiconductor chip, and in plan view to said first semiconductor chip, each of the grooves is a linear groove.
2 . The method for manufacturing the semiconductor package according to claim 1 , wherein the semiconductor package includes resin and a spacer, the method comprising:
covering the first and second semiconductor chips and a front face of the package substrate with the resin, and arranging the spacer between the first semiconductor chip and the second semiconductor chip.
3 . The method for manufacturing the semiconductor package according to claim 2 , wherein:
the spacer is a silicon substrate or a polysilicon film, a back face of the second semiconductor chip includes a gettering layer, and the semiconductor package includes a first wire and a second wire, the method comprising: electrically coupling the first semiconductor chip to the package substrate via the first wire, and electrically coupling the second semiconductor chip to the package substrate via the second wire.
4 . A method for manufacturing a semiconductor package, comprising:
forming an element layer on a front face of a semiconductor wafer, the element layer including a transistor; dicing the semiconductor wafer so as to form a first semiconductor chip, after forming the element layer; polishing a back face of the first semiconductor chip so as to form a getting layer on the back face, after dicing the semiconductor wafer; and assembling a semiconductor package which includes a package substrate, the first semiconductor chip being formed over the package substrate, after polishing the back face of the first semiconductor chip, wherein the semiconductor package includes the gettering layer, the gettering layer is a damaged layer, the damaged layer includes a plurality of grooves, a depth of each of the grooves is 2 to 3 μm, and in a plan view to said first semiconductor chip, each of the grooves is a linear groove.
5 . The method for manufacturing the semiconductor package according to claim 4 , comprising covering the first semiconductor chip and a front face of the package substrate with a resin.
6 . The method for manufacturing the semiconductor package according to claim 5 , wherein the semiconductor package includes a first wire, the method comprising electrically coupling the first semiconductor chip to the package substrate via the first wire.Join the waitlist — get patent alerts
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