Deep source electrode MOSFET

Abstract

A power semiconductor device that includes a plurality of source trenches that extend to a depth below the gate electrodes and a termination region that includes a termination trench that is as deep as the source trenches.

1 - 9 . (canceled) 
   
   
       10 . A power semiconductor device comprising:
 a semiconductor body having at least one channel region;   at least one source trench extending into said semiconductor body and being adjacent to said at least one channel region;   a gate insulation situated adjacent to said at least one source trench;   a gate electrode situated adjacent to said gate insulation;   a source electrode disposed adjacent to and insulated from said gate electrode;   a source region situated adjacent to said at least one source trench;   a source contact electrically coupled to said source electrode and said source region.   
   
   
       11 . The power semiconductor device of  claim 10 , wherein said gate electrode spans said at least one channel region. 
   
   
       12 . The power semiconductor device of  claim 10 , wherein said source contact is ohmically coupled to said at least one channel region. 
   
   
       13 . The power semiconductor device of  claim 10 , wherein said source electrode is insulated from said semiconductor body by a thick insulation layer disposed inside said at least one source trench. 
   
   
       14 . The power semiconductor device of  claim 10 , wherein said source electrode extends below said gate electrode. 
   
   
       15 . The power semiconductor device of  claim 13 , wherein said thick insulation layer is disposed below said gate electrode. 
   
   
       16 . The power semiconductor device of  claim 10  further comprising a drain contact underlying said semiconductor body. 
   
   
       17 . A power semiconductor device comprising:
 a semiconductor body having a first conductivity and including at least two channel regions, each of said at least two channel regions having a second conductivity;   at least one source trench extending into said semiconductor body and being situated between two of said at least two channel regions;   a first gate insulation situated adjacent to a first sidewall of said at least one source trench and situated adjacent to one of said least two channel regions;   a first gate electrode situated adjacent to said first gate insulation;   a second gate insulation situated adjacent to a second sidewall of said at least one source trench and situated adjacent to another of said at least two channel regions;   a second gate electrode situated adjacent to said second gate insulation;   a source electrode situated inside said at least one source trench and disposed between and insulated from said first and second gate electrodes, said source electrode extending below said first and second gate electrodes;   a source region situated adjacent to each of said first and second sidewalls of said at least one source trench;   a source contact electrically coupled to said source electrode and said source regions.   
   
   
       18 . The power semiconductor device of  claim 17 , wherein said first gate electrode spans said one of said at least two channel regions and said second gate electrode spans said another of said at least two channel regions. 
   
   
       19 . The power semiconductor device of  claim 17 , wherein said source contact is ohmically coupled to said at least two channel regions. 
   
   
       20 . The power semiconductor device of  claim 17 , wherein said source electrode is insulated from said semiconductor body by a thick insulation layer disposed inside said at least one source trench. 
   
   
       21 . The power semiconductor device of  claim 20 , wherein each of said first and second gate insulations is thinner than said thick insulation layer. 
   
   
       22 . The power semiconductor device of  claim 20 , wherein said thick insulation layer is disposed below said first and second gate electrodes. 
   
   
       23 . The power semiconductor device of  claim 17  further comprising a drain contact underlying said semiconductor body. 
   
   
       24 . A power semiconductor device comprising:
 an active region including a plurality of source trenches extending into a semiconductor body, said semiconductor body having a first conductivity;   a plurality of channel regions formed in said semiconductor body, each of said plurality of channel regions having a second conductivity, two of said plurality of channel regions being situated adjacent to each of said plurality of source trenches;   a first gate insulation situated adjacent to a first sidewall of said each of said plurality of source trenches and situated adjacent to one of said plurality of channel regions;   a first gate electrode situated adjacent to said first gate insulation;   a second gate insulation situated adjacent to a second sidewall of said each of said plurality of source trenches and situated adjacent to another of said plurality of channel regions;   a second gate electrode situated adjacent to said second gate insulation;   a source electrode situated inside said each of said plurality of source trenches and disposed between and insulated from said first and second gate electrodes, said source electrode extending below said first and second gate electrodes;   a source region situated adjacent to each of said first and second sidewalls of said each of said plurality of source trenches;   a source contact electrically coupled to said source electrode and said source region.   
   
   
       25 . The power semiconductor device of  claim 24 , wherein said source electrode is insulated from said semiconductor body by a thick insulation layer disposed inside said each of said plurality of source trenches. 
   
   
       26 . The power semiconductor device of  claim 25 , wherein each of said first and second gate insulations is thinner than said thick insulation layer inside said each of said plurality of source trenches. 
   
   
       27 . The power semiconductor device of  claim 25 , wherein said thick insulation layer is disposed below said first and second gate electrodes in said each of said plurality of source trenches. 
   
   
       28 . The power semiconductor device of  claim 24  further comprising a termination region situated adjacent to said active region, wherein said termination region includes at least one termination trench extending into said semiconductor body. 
   
   
       29 . The power semiconductor device of  claim 24  further comprising a drain contact underlying said semiconductor body.