Scribe based bond pads for integrated circuits

Abstract

An apparatus including a semiconductor substrate is disclosed. A first semiconductor die is disposed on the semiconductor substrate. A first bond out pad is disposed on the semiconductor substrate adjacent to the first semiconductor die. A first sawn semiconductor die is disposed on the semiconductor substrate adjacent to the first semiconductor die and the first bond out pad.

1 . An apparatus comprising:
 a semiconductor substrate;   a first semiconductor die disposed on the semiconductor substrate;   a first bond out pad disposed on the semiconductor substrate adjacent to the first semiconductor die; and   a first sawn semiconductor die disposed on the semiconductor substrate adjacent to the first semiconductor die and the first bond out pad.   
   
   
       2 . The apparatus of  claim 1 , wherein the first semiconductor die includes a test die. 
   
   
       3 . The apparatus of  claim 1 , wherein the first semiconductor die includes an emulation die. 
   
   
       4 . The apparatus of  claim 1 , wherein the bond out pad is disposed between the first semiconductor die and the first sawn semiconductor die. 
   
   
       5 . The apparatus of  claim 1 , wherein the first bond out pad is disposed along a first scribe line of the semiconductor substrate and completely within a scribe area of the semiconductor substrate. 
   
   
       6 . The apparatus of  claim 1 , comprising a second sawn semiconductor die disposed on the semiconductor substrate adjacent to the first semiconductor die. 
   
   
       7 . The apparatus of  claim 6 , comprising a second bond out pad disposed on the semiconductor substrate between the first semiconductor die and the second sawn semiconductor die. 
   
   
       8 . The apparatus of  claim 6 , wherein the second bond out pad is disposed along a second scribe line of the semiconductor substrate and completely within a scribe area of the semiconductor substrate. 
   
   
       9 . The apparatus of  claim 1 , comprising test circuitry disposed on the semiconductor substrate outside the first semiconductor die. 
   
   
       10 . The apparatus of  claim 1 , wherein the first semiconductor die includes a microprocessor. 
   
   
       11 . The apparatus of  claim 1 , wherein the first semiconductor die includes read only memory. 
   
   
       12 . The apparatus of  claim 1 , comprising electrostatic damage protection circuitry disposed under the first bond out pad. 
   
   
       13 . An apparatus comprising:
 a portion of a semiconductor wafer;   a first semiconductor die disposed on the portion of the semiconductor wafer;   a first bond out pad disposed adjacent to the first semiconductor die on the portion of the semiconductor wafer; and   a first sawn semiconductor die disposed adjacent to the first bond out pad and at a first edge of the portion of the semiconductor wafer, wherein a part of the first sawn semiconductor die forms at least a portion of the first edge.   
   
   
       14 . The apparatus of  claim 13 , wherein the first semiconductor die includes a test die. 
   
   
       15 . The apparatus of  claim 13 , comprising a second sawn semiconductor die disposed adjacent to the first semiconductor die and at a second edge of the portion of the semiconductor wafer, wherein a part of the second sawn semiconductor die forms at least a portion of the second edge. 
   
   
       16 . The apparatus of  claim 15 , comprising a second bond out pad disposed between the first semiconductor die and the second sawn semiconductor die. 
   
   
       17 . The apparatus of  claim 13 , comprising test circuitry disposed on the portion of a semiconductor wafer and adjacent the first semiconductor die. 
   
   
       18 . A sawn semiconductor wafer structure comprising:
 a first sawn edge and a second sawn edge;   a test die disposed between the first and second sawn edges;   a first bond out pad disposed adjacent to the test die; and   a first sawn semiconductor die disposed adjacent to the first bond out pad and at the first sawn edge, wherein at least a portion of the first sawn edge is a part of the first sawn semiconductor die.   
   
   
       19 . The sawn semiconductor wafer structure of  claim 18 , comprising a second sawn semiconductor die disposed adjacent to the test die and at the second sawn edge, wherein at least a portion of the second sawn edge is a part of the second sawn semiconductor die. 
   
   
       20 . The sawn semiconductor wafer structure of  claim 19 , comprising a second bond out pad disposed between the test die and the second sawn semiconductor die.