Conductive hard mask to protect patterned features during trench etch

Abstract

A monolithic three dimensional memory array is formed by a method that includes forming a first memory level above a substrate by i) forming a plurality of first substantially parallel conductors extending in a first direction, ii) forming first pillars above the first conductors, each first pillar comprising a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, iii) depositing a first dielectric layer above the first pillars, and iv) etching a plurality of substantially parallel first trenches in the first dielectric layer, the first trenches extending in a second direction, wherein, after the etching step, the lowest point in the trenches is above the lowest point of the first conductive layer or layerstack, wherein the first conductive layer or layerstack does not comprise a resistivity-switching metal oxide or nitride. The method also includes monolithically forming a second memory level above the first memory level. Other aspects are also described.

1 . A method for forming a monolithic three dimensional memory array, the method comprising:
 a) forming a first memory level above a substrate by a method comprising:
 i) forming a plurality of first substantially parallel conductors extending in a first direction; 
 ii) forming first pillars above the first conductors, each first pillar comprising a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step; 
 iii) depositing a first dielectric layer above the first pillars; 
 iv) etching a plurality of substantially parallel first trenches in the first dielectric layer, the first trenches extending in a second direction, wherein, after the etching step, a lowest point in the trenches is above a lowest point of the first conductive layer or layerstack, wherein the first conductive layer or layerstack does not comprise a resistivity-switching metal oxide or nitride; and 
   b) monolithically forming a second memory level above the first memory level.   
   
   
       2 . The method of  claim 1 , further comprising:
 filling the first trenches with a second conductive material; and   planarizing to remove overfill of the second conductive material to form a plurality of substantially parallel second conductors.   
   
   
       3 . The method of  claim 2 , wherein each first pillar is vertically disposed between one of the first conductors and one of the second conductors. 
   
   
       4 . The method of  claim 3 , wherein each of the second conductors is electrically in contact with the first conductive layer or layerstack of at least one of the first pillars. 
   
   
       5 . The method of  claim 3 , wherein the first memory level comprises a plurality of first memory cells, each first memory cell comprising a portion of one of the first conductors, one of the first pillars, and a portion of one of the second conductors. 
   
   
       6 . The method of  claim 2 , wherein the second conductors comprise a metal or metal alloy. 
   
   
       7 . The method of  claim 6 , wherein the metal or metal alloy comprise tungsten, copper, aluminum, or alloys thereof. 
   
   
       8 . The method of  claim 1 , wherein the second direction is substantially perpendicular to the first direction. 
   
   
       9 . The method of  claim 1 , wherein the vertically oriented diodes of the first pillars comprise silicon, germanium, or an alloy of silicon and/or germanium. 
   
   
       10 . The method of  claim 1 , further comprising annealing the silicon, germanium or alloy of silicon and/or germanium to form polycrystalline diodes. 
   
   
       11 . The method of  claim 1 , wherein the vertically oriented diodes of the first pillars are semiconductor junction diodes. 
   
   
       12 . The method of  claim 11 , wherein the semiconductor junction diodes comprise p-i-n diodes. 
   
   
       13 . The method of  claim 1 , wherein the first conductive layer or layerstack comprises a metal or metal alloy. 
   
   
       14 . The method of  claim 13 , wherein the metal or metal alloy comprises tungsten or a tungsten alloy. 
   
   
       15 . The method of  claim 14 , wherein the metal or metal alloy comprises tungsten deposited by sputtering. 
   
   
       16 . The method of  claim 1 , wherein the substrate comprises monocrystalline silicon. 
   
   
       17 . The method of  claim 1 , wherein forming the first pillars comprises:
 depositing a layer of semiconductor material;   depositing the first conductive layer or layerstack above the layer of semiconductor material, wherein the layer of semiconductor material has not been etched;   patterning and etching the first conductive layer or layerstack; and   etching the layer of semiconductor material, wherein the etched first conductive layer or layerstack serves as a hard mask.   
   
   
       18 . A first memory level formed above a substrate, the first memory level comprising:
 a plurality of substantially parallel, substantially coplanar bottom conductors extending in a first direction;   a plurality of substantially parallel, substantially coplanar top conductors extending in a second direction different from the first direction, the top conductors above the bottom conductors; and   a plurality of first pillars, each first pillar vertically disposed between one of the bottom conductors and one of the top conductors, each first pillar comprising a vertically oriented diode and a conductive layer or layerstack, the conductive layer or layerstack above the vertically oriented diode,   wherein the conductive layer or layerstack of each first pillar is in contact with one of the top conductors, and   wherein the conductive layer or layerstack comprises a layer of a metal or a metal alloy.   
   
   
       19 . The first memory level of  claim 18 , wherein the metal or metal alloy comprises tungsten or a tungsten alloy. 
   
   
       20 . The first memory level of  claim 18 , wherein the vertically oriented diode of each of the first pillars comprises a semiconductor junction diode. 
   
   
       21 . The first memory level of  claim 20 , wherein the vertically oriented diode of each of the first pillars comprises a p-i-n diode. 
   
   
       22 . The first memory level of  claim 20 , wherein the vertically oriented diodes comprise polycrystalline semiconductor material. 
   
   
       23 . The first memory level of  claim 22 , wherein the polycrystalline semiconductor material comprises silicon, germanium, or an alloy of silicon and/or germanium. 
   
   
       24 . The first memory level of  claim 18 , wherein the top conductors are formed by a Damascene method. 
   
   
       25 . The first memory level of  claim 18 , wherein the substrate comprises monocrystalline silicon. 
   
   
       26 . The first memory level of  claim 18 , wherein the bottom conductors comprise tungsten or a tungsten alloy. 
   
   
       27 . The first memory level of  claim 18 , wherein at least a second memory level is monolithically formed above the first memory level, the first and second memory levels both in a monolithic three dimensional memory array. 
   
   
       28 . The first memory level of  claim 18 , further comprising nonvolatile memory cells, wherein each memory cell comprises one of the first pillars, a portion of one of the top conductors, and a portion of one of the bottom conductors. 
   
   
       29 . A monolithic three dimensional memory array comprising:
 a) a first memory level above a substrate, the first memory level comprising:
 i) a plurality of substantially parallel, substantially coplanar bottom conductors extending in a first direction; 
 ii) a plurality of substantially parallel, substantially coplanar top conductors extending in a second direction different from the first direction, the top conductors above the bottom conductors; and 
 iii) a plurality of first pillars, each first pillar vertically disposed between one of the bottom conductors and one of the top conductors, each first pillar comprising a vertically oriented diode and a conductive layer or layerstack, the conductive layer or layerstack above the vertically oriented diode, 
 wherein the conductive layer or layerstack of each first pillar is in contact with one of the top conductors, wherein the conductive layer or layerstack comprises a layer of a metal or a metal alloy; and 
   b) a second memory level monolithically formed above the first memory level.   
   
   
       30 . The monolithic three dimensional memory array of  claim 29 , wherein the metal or metal alloy comprises tungsten or a tungsten alloy. 
   
   
       31 . The monolithic three dimensional memory array of  claim 29 , wherein the vertically oriented diode of each of the first pillars comprises a semiconductor junction diode. 
   
   
       32 . The monolithic three dimensional memory array of  claim 31 , wherein the vertically oriented diode of each of the first pillars comprises a p-i-n diode. 
   
   
       33 . The monolithic three dimensional memory array of  claim 29 , wherein the vertically oriented diode of each of the first pillars comprise polycrystalline semiconductor material. 
   
   
       34 . The monolithic three dimensional memory array of  claim 33 , wherein the polycrystalline semiconductor material comprises silicon, germanium, or an alloy of silicon and/or germanium. 
   
   
       35 . The monolithic three dimensional memory array of  claim 29 , wherein the top conductors are formed by a Damascene method. 
   
   
       36 . The monolithic three dimensional memory array of  claim 29 , wherein the substrate comprises monocrystalline semiconductor material.