Trench gate type semiconductor device and method of producing the same

Abstract

A method of producing a trench gate type MOSFET is provided in which each intersection trench is formed as a two-stage trench structure. A gate trench is backfilled with a mask material and the mask material is then patterned to form a mask used for forming each intersection trench. The intersection trench intersecting the gate trench is provided so as to be deeper than the gate trench. A Schottky electrode is provided in the bottom of each intersection trench 10 p . In this manner, there is provided a trench gate type semiconductor device and a method of producing the same, in which: the cell pitch can be reduced even when a wide band gap semiconductor is used as a main semiconductor substrate; good ohmic contacts can be obtained; and an excessive electric field is prevented from being applied to an insulating film in the bottom of each trench.

1 . A method of producing a trench gate type semiconductor device, comprising the steps of:
 (I) laminating a voltage withstanding layer of a wide band gap semiconductor of a first conductivity type and a body layer of a wide band gap semiconductor of a second conductivity type successively on a wide band gap semiconductor substrate with a high impurity concentration by epitaxially growing the voltage withstanding layer and the body layer respectively on the whole area of a surface of the semiconductor substrate;   (II) forming a first mask having first opening portions on a surface of the body layer;   (III) forming source ion-implanted regions by ion implantation from the first opening portions;   (IV) depositing a second mask having a thickness smaller than one second as large as the width of each first opening portion, on the whole area of the surface of the semiconductor substrate after the step (III) and performing anisotropic etching to provide second opening portions in the second mask on the respective bottoms of the first opening portions;   (V) pderforming anisotropic etching from the second opening portions to form first trenches each of which passes through the corresponding source ion-implanted region and the body layer and reaches the voltage withstanding layer; and   (VI) forming an insulating film on an inner wall surface of each first trench and embedding a gate electrode in the first trench so as to be located opposite to the corresponding source ion-implanted region, the body layer and the voltage withstanding layer respectively through the insulating film.   
     
     
         2 . A method of producing a trench gate type semiconductor device, comprising the steps of:
 (I) laminating a voltage withstanding layer of a wide band gap semiconductor of a first conductivity type, a body layer of a wide band gap semiconductor of a second conductivity type and a body contact layer of a wide band gap semiconductor of the second conductivity type having a high impurity concentration surface capable of obtaining practical ohmic contact successively on a wide band gap semiconductor substrate with a high impurity concentration by epitaxially growing the voltage withstanding layer, the body layer and the body contact layer respectively on the whole area of a surface of the semiconductor substrate;   (II) forming a first mask having first opening portions on a surface of the body contact layer;   (IIIa) performing anisotropic etching from the first opening portions to form first trenches each of which passes through the body contact layer and has a bottom in the body layer;   (IIIb) performing ion implantation in the respective bottoms of first trenches or epitaxial growth on the respective bottoms of the first trenches to form source ion-implanted regions of the first conductivity type in a position at least deeper than the body contact layer;   (IV) depositing a second mask having a thickness smaller than one second as large as the width of each first trench, on the whole area of the surface of the semiconductor substrate after the step (IIIb) and performing anisotropic etching to provide second opening portions in the second mask on the respective bottoms of the first trenches;   (V) performing anisotropic etching from the second opening portions to form second trenches each of which reaches the voltage withstanding layer; and   (VI) forming an insulating film on an inner wall surface of each second trench and embedding a gate electrode in the second trench so as to be located opposite to the corresponding source ion-implanted region, the body layer and the voltage withstanding layer respectively through the insulating film.   
     
     
         3 . A method of producing a trench gate type semiconductor device, comprising the steps of:
 (I) laminating a voltage withstanding layer of a wide band gap semiconductor of a first conductivity type, a body layer of a wide band gap semiconductor of a second conductivity type and a body contact layer of a wide band gap semiconductor of the second conductivity type having a high impurity concentration surface capable of obtaining practical ohmic contact successively on a wide band gap semiconductor substrate with a high impurity concentration by epitaxially growing the voltage withstanding layer, the body layer and the body contact layer respectively on the whole area of a surface of the semiconductor substrate;   (II) forming a first mask having first opening portions on a surface of the body contact layer;   (IIIa) performing anisotropic etching from the first opening portions to form first trenches each of which passes through the body contact layer and has a bottom in the body layer;   (IIIb) performing ion implantation in the respective bottoms of the first trenches or epitaxial growth on the respective bottoms of the first trenches to form source ion-implanted regions of the first conductivity type in a position at least deeper than the body contact layer;   (IVa) depositing a second mask having a thickness smaller than one second as large as the width of each first trench, on the whole area of the surface of the semiconductor substrate after the step (IIIb) and performing anisotropic etching to provide second opening portions in the second mask on the respective bottoms of the first trenches;   (IVb) performing anisotropic etching from the second opening portions to form third trenches each of which has a bottom in the corresponding source ion-implanted region;   (IVc) performing ion implantation in the respective bottoms of the third trenches or epitaxial growth on the respective bottoms of the third trenches to form source elongation ion-implanted regions at least deeper than the source ion-implanted regions;   (IVd) depositing a third mask having a thickness smaller than one second as large as the width of each third trench, on the whole area of the surface of the semiconductor substrate after the step (IVc) and performing anisotropic etching to provide third opening portions in the third mask on the respective bottoms of the third trenches;   (V) performing anisotropic etching from the third opening portions to form second trenches each of which reaches the voltage withstanding layer; and   (VI) forming an insulating film on an inner wall surface of each second trench and embedding a gate electrode in the second trench so as to be located opposite to the corresponding source elongation ion-implanted region, the body layer and the voltage withstanding layer respectively through the insulating film.   
     
     
         4 . A method of producing a trench gate type semiconductor device according to  claim 2 , wherein:
 the step (IIIb) is replaced by a step of performing ion implantation in the respective bottoms of the first trenches or epitaxial growth on the respective bottoms of the first trenches to form source contact ion-implanted regions of the first conductivity type on a surface side having a high impurity concentration surface capable of obtaining ohmic contact and source extension ion-implanted regions of the first conductivity type on a lower layer side so as to be located at least deeper than the body contact layer; and   the step (VI) is replaced by a step of forming an insulating film on an inner wall surface of each second trench and embedding a gate electrode in the second trench so as to be located opposite to the corresponding source extension ion-implanted region, the corresponding body region and the voltage withstanding layer respectively through the insulating film.   
     
     
         5 . A method of producing a trench gate type semiconductor device according to  claim 3 , wherein:
 the step (IIIb) is replaced by a step of performing ion implantation in the respective bottoms of the first trenches or epitaxial growth on the respective bottoms of the first trenches to form source contact ion-implanted regions of the first conductivity type on a surface side having a high impurity concentration surface capable of obtaining ohmic contact and source extension ion-implanted regions of the first conductivity type on a lower layer side so as to be located at least deeper than the body contact layer; and   the step (IVc) is replaced by a step of performing ion implantation in the respective bottoms of the third trenches or epitaxial growth on the respective bottoms of the third trenches to form source elongation ion-implanted regions of the first conductivity type which are at least in contact with the source extension ion-implanted regions respectively.   
     
     
         6 . A method of producing a trench gate type semiconductor device according to  claim 2  or  claim 4 , wherein a step (Va) of performing heat treatment at a temperature where the function of the first mask is not spoiled and where ions implanted in the source contact regions cannot be activated perfectly but the source contact regions can be prevented from being degenerated by the following steps is inserted between the steps (V) and (VI). 
     
     
         7 . A method of producing a trench gate type semiconductor device according to  claim 3  or  claim 5 , wherein a step (Va) of performing heat treatment at a temperature where the function of the third mask is not spoiled and where ions implanted in the source extension ion-implanted regions cannot be activated perfectly but the source extension ion-implanted regions can be prevented from being degenerated by the following steps is inserted between the steps (V) and (VI). 
     
     
         8 . A method of producing a trench gate type semiconductor device according to  claim 6 , wherein:
 each of the first to third masks contains silicon dioxide as a main component; and   the temperature for heat treatment in the step (Va) is not higher than 1350° C.   
     
     
         9 . A method of producing a trench gate type semiconductor device according to  claim 6 , wherein:
 the semiconductor substrate contains hexagonal silicon carbide as a main semiconductor material; and   the temperature for heat treatment in the step (Va) is not lower than 1250° C.   
     
     
         10 . A method of producing a trench gate type semiconductor device according to  claim 6 , wherein a step of forming a selectively releasable cap material containing carbon or silicon nitride at least on any one of the semiconductor substrate, the first mask and the third mask is provided before the heat treatment in the step (Va). 
     
     
         11 . A method of producing a trench gate type semiconductor device according to  claim 10 , wherein the semiconductor substrate contains silicon carbide as a main semiconductor material. 
     
     
         12 . A trench gate type semiconductor device comprising:
 a wide band gap semiconductor substrate with a high impurity concentration;   a voltage withstanding layer of a wide band gap semiconductor of a first conductivity type with a low impurity concentration which is provided on one principal surface of the semiconductor substrate;   body regions of a wide band gap semiconductor of a second conductivity type which are higher in impurity concentration than the voltage withstanding layer and which are provided on the voltage withstanding layer;   body contact regions of the second conductivity type each of which is a selective region having a high impurity concentration surface capable of obtaining ohmic contact and each of which is provided in a surface layer of the corresponding body region;   source contact regions of the first conductivity type each of which is a selective region having a high impurity concentration surface capable of obtaining ohmic contact and each of which is provided in the surface layer of the corresponding body region;   source extension regions of the first conductivity type each of which is provided as a layer under the corresponding source contact region;   trenches each of which extends from a surface of the corresponding source contact region to the voltage withstanding layer while passing through the corresponding source contact region, the corresponding source extension region and the corresponding body region;   insulating films each of which is provided on an inner wall surface of the corresponding trench; and   gate electrodes each of which is embedded in the corresponding trench so as to be located opposite to the corresponding source extension region, the corresponding body region and the voltage withstanding layer through the corresponding insulating film; wherein:   each of the trenches includes a first trench which is wide, and a second trench which is made narrower than the first trench by the thickness of a first mask provided on a side wall surface of the first trench so that the second trench opens in the bottom of the first trench;   each of the second trenches has such a depth that the second trench reaches the voltage withstanding layer while passing through the corresponding source contact region, the corresponding source extension region and the corresponding body region provided below the bottom of the corresponding first trench;   the gate electrodes are provided in the second trenches respectively through insulating films provided on respective inner wall surfaces of the second trenches; and   interlayer insulating films are provided in the second trenches respectively so that respective upper portions of the gate electrodes are covered with the interlayer insulating films respectively.   
     
     
         13 . A trench gate type semiconductor device according to  claim 12 , wherein:
 each third trench is provided between the corresponding first trench and the corresponding second trench;   each of the third trenches has a structure in which the third trench is made narrower than the first trench by the thickness of a first mask provided on a side wall surface of the first trench so that the third trench opens in the bottom of the first trench and in which the second trench is made narrower than the third trench by the thickness of a second mask provided on a side wall surface of the third trench so that the second trench opens in the bottom of the third trench;   each of the third trenches has such a depth that the third trench reaches the corresponding source extension region on a lower layer side while passing through the corresponding source contact region on a surface side provided below the bottom of the first trench;   source elongation regions provided below the respective bottoms of the third trenches are in contact with the source extension regions respectively; and   the second trenches are provided in the respective bottoms of the third trenches.   
     
     
         14 . A trench gate type semiconductor device according to  claim 12  or  13 , wherein the semiconductor substrate contains silicon carbide as a main semiconductor material. 
     
     
         15 . A trench gate type semiconductor device according to  claim 14 , wherein elements are added simultaneously at epitaxial growth so that each body contact region effectively contains aluminum with an impurity concentration of 2×10 19  cm −3  or higher. 
     
     
         16 . A trench gate type semiconductor device according to  claim 14 , wherein each source contact region or at least a surface region of each source contact region is doped with phosphorus while a remaining part of each source ion-implanted region is doped with nitrogen or each source extension region and each source elongation region are doped with nitrogen. 
     
     
         17 . A trench gate type semiconductor device according to  claim 14 , wherein the principal surface of the semiconductor substrate is substantially a (000-1) C-face of a hexagonal silicon carbide semiconductor. 
     
     
         18 . A trench gate type semiconductor device according to  claim 12  or  13 , wherein the semiconductor substrate contains any one of gallium nitride, aluminum nitride and a alloy of gallium nitride and aluminum nitride as a main component. 
     
     
         19 . A trench gate type semiconductor device according to  claim 14 , wherein each body contact region includes a quantum well structure suitable for obtaining ohmic contact. 
     
     
         20 . A trench gate type semiconductor device comprising:
 a wide band gap semiconductor substrate with a high impurity concentration;   a voltage withstanding layer of a wide band gap semiconductor of a first conductivity type with a low impurity concentration which is provided on one principal surface of the semiconductor substrate;   body regions of a wide band gap semiconductor of a second conductivity type which are higher in impurity concentration than the voltage withstanding layer and which are provided on the voltage withstanding layer;   body contact regions of the second conductivity type each of which is a selective region having a high impurity concentration surface capable of obtaining ohmic contact and each of which is provided in a surface layer of the corresponding body region;   source contact regions of the first conductivity type each of which is a selective region having a high impurity concentration surface capable of obtaining ohmic contact and each of which is provided in the surface layer of the corresponding body region;   source extension regions of the first conductivity type each of which is provided as a layer under the corresponding source contact region;   trenches each of which extends from a surface of the corresponding source contact region to the voltage withstanding layer while passing through the corresponding source contact region, the corresponding source extension region and the corresponding body region;   insulating films each which is provided on an inner wall surface of the corresponding trench;   gate electrodes each of which is embedded in the corresponding trench so as to be located opposite to the corresponding source extension region, the corresponding body region and the voltage withstanding layer through the corresponding insulating film;   a first main electrode which is in contact with respective surfaces of the body contact regions of the second conductivity type and the source contact regions of the first conductivity type; and   a second main electrode which is in contact with the other principal surface of the semiconductor substrate; wherein the trench gate type semiconductor device further comprises:   intersection trenches which have intersection portions intersecting with the trenches, and other portions deeper than the trenches; and   Schottky electrodes which are embedded in the intersection trenches so as to be electrically insulated from the gate electrodes and which are in Schottky contact with surfaces of the voltage withstanding layer exposed in the respective bottoms of the intersection trenches.   
     
     
         21 . A trench gate type semiconductor device according to  claim 20 , wherein:
 each of the trenches includes a first trench which is wide, and a second trench which is made narrower than the first trench by the thickness of a first mask provided on a side wall surface of the first trench so that the second trench opens in the bottom of the first trench;   each of the second trenches has such a depth that the second trench reaches the voltage withstanding layer while passing through the corresponding source contact region, the corresponding source extension region and the corresponding body region provided below the bottom of the corresponding first trench;   the gate electrodes are provided in the second trenches respectively through insulating films provided on respective inner wall surfaces of the second trenches; and   interlayer insulating films are provided in the second trenches respectively so that respective upper portions of the gate electrodes are covered with the interlayer insulating films respectively.   
     
     
         22 . A trench gate type semiconductor device according to  claim 20 , wherein the Schottky electrodes are electrically short-circuited to the first main electrode. 
     
     
         23 . A trench gate type semiconductor device according to  claim 20 , wherein a relative dielectric constant-dielectric breakdown electric field product which is the product of the relative dielectric constant and the dielectric breakdown electric field of the semiconductor substrate near the bottom of each trench is larger than a relative dielectric constant-dielectric breakdown electric field product which is the product of the relative dielectric constant and the normal maximum electric field of each insulating film. 
     
     
         24 . A trench gate type semiconductor device according to  claim 23 , wherein:
 each insulating film contains silicon dioxide as a main component; and   the relative dielectric constant-dielectric breakdown electric field product of the semiconductor substrate is not smaller than 12MV/cm.   
     
     
         25 . A trench gate type semiconductor device according to  claim 23  or  24 , wherein:
 the semiconductor substrate contains silicon carbide as a main semiconductor material; and   the relative dielectric constant-dielectric breakdown electric field product of each insulating film is not larger than 25MV/cm.   
     
     
         26 . A trench gate type semiconductor device according to  claim 25 , wherein the silicon carbide as the main semiconductor material of the semiconductor substrate is 4H-silicon carbide. 
     
     
         27 . A trench gate type semiconductor device according to  claim 26 , wherein the Schottky electrodes are selected so that leakage current density at maximum allowable temperature, obtained under an electric field not lower than the dielectric breakdown electric field of the semiconductor substrate by the Schottky barrier height of a portion of each Schottkey electrode being in Schottky contact with the voltage withstanding layer surface exposed in the bottom of the corresponding intersection trench is not higher than 10 −5  A/cm 2 . 
     
     
         28 . A trench gate type semiconductor device according to  claim 27 , wherein the Schottky barrier height is not lower than 1.85 eV. 
     
     
         29 . A trench gate type semiconductor device according to  claim 28 , wherein a metal forming the Schottky barrier contains either of platinum and platinum silicide as a main component. 
     
     
         30 . A trench gate type semiconductor device according to  claim 29 , wherein:
 the first main electrode contains nickel as an effective component; and   the Schottky electrodes containing either of platinum and platinum silicide as a main component are connected to the nickel-containing first main electrode through the barrier metal so as not to be in direct contact with the first main electrode.   
     
     
         31 . A trench gate type semiconductor device according to  claim 20 , wherein the one principal surface of the semiconductor substrate is substantially a (000-1) C-face of a 4H-silicon carbide semiconductor. 
     
     
         32 . A trench gate type semiconductor device according to  claim 31 , wherein the width of each intersection trench is larger than the width of each trench. 
     
     
         33 . A method of producing a trench gate type semiconductor device according to  claim 2 , further comprising the steps of:
 forming intersection trenches after the step of (V) forming the second trenches; and   forming Schottky electrodes in at least part of respective inner surfaces of the intersection trenches.   
     
     
         34 . A method of producing a trench gate type semiconductor device according to  claim 33 , further comprising the steps of:
 embedding the second mask in the intersection trenches after the step of forming the intersection trenches;   removing the first mask while leaving the second mask;   embedding gate electrodes in respective inner surfaces of the second trenches through gate insulating films and embedding interlayer insulating films on the gate electrodes respectively; and   removing the second mask before the step of forming Schottky electrodes in at least part of respective inner surfaces of the intersection trenches.   
     
     
         35 . A method of producing a trench gate type semiconductor device according to  claim 34 , wherein the step of embedding gate electrodes in respective inner surfaces of the second trenches through gate insulating films and embedding interlayer insulating films on the gate electrodes respectively is provided before the step of forming the intersection trenches. 
     
     
         36 . A method of producing a trench gate type semiconductor device according to  claim 35 , further comprising the steps of; forming etch stop films containing silicon nitride as a main component on the interlayer insulating films after the step of forming the interlayer insulating films, backfilling the second trenches and the first trenches with silicon dioxide as a main component. 
     
     
         37 . A method of producing a trench gate type semiconductor device according to  claim 34 , further comprising the steps of:
 removing the first mask after the step of forming the intersection trenches;   embedding a fourth mask selectively in the intersection trenches;   embedding gate electrodes in respective inner surfaces of the second trenches through gate insulating films and embedding interlayer insulating films in the second trenches on the gate electrodes; and   removing the fourth mask before the step of forming Schottky electrodes in at least part of respective inner surfaces of the intersection trenches.   
     
     
         38 . A method of producing a trench gate type semiconductor device according to  claim 34 , further comprising the step of smoothening the shape of each intersection trench or reducing the surface roughness of the inner surface of each intersection trench after the step of removing the first mask. 
     
     
         39 . A method of producing a trench gate type semiconductor device according to  claim 37  or  38 , wherein the step of embedding a fourth mask selectively in the intervention trenches includes the steps of:
 embedding a fifth mask selectively in the second trenches;   depositing a fourth mask on the one principal surface;   etching back the fourth mask to leave the fourth mask only in the inside of each intersection trench; and   removing the fifth mask.   
     
     
         40 . A method of producing a trench gate type semiconductor device according to  claim 34  or  37 , wherein:
 the first mask contains silicon dioxide as a main component; and   the second or fourth mask contains silicon nitride as a main component.   
     
     
         41 . A method of producing a trench gate type semiconductor device according to  claim 39 , wherein the fifth mask contains silicon dioxide as a main component. 
     
     
         42 . A method of producing a trench gate type semiconductor device according to  claim 41 , wherein the step of embedding a fifth mask selectively in the second trenches includes the steps of:
 depositing polycrystalline silicon on the one principal surface;   etching back the polycrystalline silicon to leave the polycrystalline silicon in the inside of each second trench narrower than each intersection trench; and   thermally oxidizing part of the polycrystalline silicon.   
     
     
         43 . A method of producing a trench gate type semiconductor device according to  claim 42 , further comprising the step of providing a screen oxide film on the inner surface of each second trench before the step of depositing polycrystalline silicon on the one principal surface. 
     
     
         44 . A method of producing a trench gate type semiconductor device according to  claim 38 , wherein the step of smoothening the shape or reducing the surface roughness of the inner surface of each intersection trench includes at least one of first and second heat-treating steps, the first heat-treating step for heat-treating the semiconductor substrate at a temperature of 1600° C. to 1800° C., both inclusively, in an inert gas atmosphere or in a silane-containing inert gas atmosphere after formation of the intersection trenches, and the second heat-treating step for heat-treating the semiconductor substrate in a temperature of 1400° C. to 1500° C., both inclusively, in a hydrogen atmosphere. 
     
     
         45 . A method of producing a trench gate type semiconductor device according to  claim 44 , wherein the semiconductor substrate contains silicon carbide as a main semiconductor material. 
     
     
         46 . A method of producing a trench gate type semiconductor device according to  claim 33 , wherein:
 the semiconductor substrate contains 4H-silicon carbide as a main semiconductor material;   each of the Schottky electrodes contains platinum silicide as a component effective in forming a Schottky barrier; and   the step of forming the Schottky electrodes includes the steps of:   depositing platinum on the semiconductor substrate; and   etching back the platinum to thereby embed the platinum in each of the intersection trenches.   
     
     
         47 . A method of producing a trench gate type semiconductor device according to  claim 33 , wherein:
 the semiconductor substrate contains 4H-silicon carbide as a main semiconductor material;   each of the Schottky electrodes contains platinum silicide as a component effective in forming a Schottky barrier; and   the step of forming the Schottky electrodes includes the steps of:   depositing platinum on the semiconductor substrate;   heat-treating the semiconductor substrate to cause a reaction between part of the deposited platinum and the semiconductor substrate to thereby produce platinum silicide; and   removing an unreacted part of the deposited platinum.   
     
     
         48 . A method of producing a trench gate type semiconductor device according to  claim 47 , further comprising the step of depositing a metal easy to produce carbide so as to be in contact with the platinum, the step being provided after the step of depositing the platinum and before the step of performing heat treatment to form the platinum silicide. 
     
     
         49 . A method of producing a trench gate type semiconductor device according to  claim 48 , wherein the metal easy to produce carbide is any metal selected from all elements in groups  4  through  6  on the periodic table of elements. 
     
     
         50 . A method of producing a trench gate type semiconductor device according to  claim 49 , wherein the metal easy to produce carbide is titanium. 
     
     
         51 . A method of producing a trench gate type semiconductor device according to  claim 49 , further comprising: the step of etching back the platinum silicide at least below the bottom of each of the first trenches, the step being provided before application of nickel and after the step of performing heat treatment to form the platinum silicide after the titanium is deposited. 
     
     
         52 . A method of producing a trench gate type semiconductor device according to  claim 50 , wherein an electrode film containing nickel common with the first main electrode is laminated on the platinum silicide film effective in forming a Schottky barrier, through a barrier metal film. 
     
     
         53 . A method of producing a trench gate type semiconductor device according to  claim 7 , wherein:
 each of the first to third masks contains silicon dioxide as a main component; and   the temperature for heat treatment in the step (Va) is not higher than 1350° C.   
     
     
         54 . A method of producing a trench gate type semiconductor device according to  claim 7 , wherein:
 the semiconductor substrate contains hexagonal silicon carbide as a main semiconductor material; and   the temperature for heat treatment in the step (Va) is not lower than 1250° C.   
     
     
         55 . A method of producing a trench gate type semiconductor device according to  claim 6 , wherein a step of forming a selectively releasable cap material containing carbon or silicon nitride at least on any one of the semiconductor substrate, the first mask and the third mask is provided before the heat treatment in the step (Va).