Apparatus For Storing Instructions In A Multithreading Microprocessor

Abstract

A circuit for selecting one of N requesters in a round-robin fashion is disclosed. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the requestors is selected next. The first addend is an N-bit vector where each bit is false if the corresponding requester is requesting access to a shared resource. The second addend is a 1-hot vector indicating the last selected requestor. A multithreading microprocessor dispatch scheduler employs the circuit for N concurrent threads each thread having one of P priorities. The dispatch scheduler generates P N-bit 1-hot round-robin bit vectors, and each thread's priority is used to select the appropriate round-robin bit from P vectors for combination with the thread's priority and an issuable bit to create a dispatch level used to select a thread for instruction dispatching.

1 . A multithreading processor configured to concurrently execute a plurality of instruction threads, comprising:
 at least one skid buffer coupled between an instruction fetch pipeline and an execution pipeline, the at least one skid buffer configured to store at least one instruction of the plurality of instruction threads dispatched to the execution pipeline,   wherein the at least one skid buffer is configured to re-issue at least one instruction flushed from the execution pipeline to avoid re-fetching the at least one flushed instruction from the instruction fetch pipeline.   
   
   
       2 . The processor of  claim 1 , wherein each of the at least one skid buffer corresponds to a respective thread context. 
   
   
       3 . The processor of  claim 1 , wherein each of the at least one skid buffer comprises:
 a plurality of entries configured to store an instruction, and   an associated valid bit to indicate whether the associated instruction is valid.   
   
   
       4 . The processor of  claim 1 , wherein the at least one skid buffer is configured as a circular queue of entries. 
   
   
       5 . The processor of  claim 1 , wherein the at least one skid buffer is configured to receive a write signal each time an instruction is written into the at least one skid buffer. 
   
   
       6 . The processor of  claim 1 , further comprising control logic, coupled to the at least one skid buffer, configured to control a plurality of counters associated with the at least one skid buffer. 
   
   
       7 . The processor of  claim 6 , wherein the control logic is configured to control a full count counter and generate a full signal to indicate that a skid buffer is full. 
   
   
       8 . The processor of  claim 6 , wherein the control logic is configured to control an empty count counter and generate an empty signal to indicate that a skid buffer is empty. 
   
   
       9 . The processor of  claim 6 , wherein the control logic is configured to update a valid bit of the at least one skid buffer. 
   
   
       10 . The processor of  claim 6 , wherein the control logic is configured to control a commit pointer that specifies a next instruction to be committed and is incremented by a thread context (TC) committed signal. 
   
   
       11 . The processor of  claim 6 , wherein the control logic is configured to remove an instruction from the at least one skid buffer based on a signal from an execution pipeline. 
   
   
       12 . An apparatus in a multithreading processor configured to concurrently execute a plurality of threads of execution, comprising:
 at least one skid buffer coupled between an instruction fetch pipeline and an instruction execution pipeline, the at least one skid buffer configured to store instructions of the plurality of threads after being dispatched to the instruction execution pipeline,   wherein the at least one skid buffer is configured to re-issue instructions flushed from the instruction execution pipeline to avoid re-fetching the flushed instructions from the instruction fetch pipeline.   
   
   
       13 . A method for storing instructions in a multithreading processor configured to concurrently execute a plurality of instruction threads, comprising:
 storing in a skid buffer at least one instruction of the plurality of instruction threads that has dispatched to an execution pipeline from an instruction fetch pipeline; and   re-issuing from the skid buffer at least one instruction flushed from the execution pipeline to avoid re-fetching the at least one flushed instruction from the instruction fetch pipeline.   
   
   
       14 . The method of  claim 13 , further comprising associating each of the at least one skid buffer with a respective thread context. 
   
   
       15 . The method of  claim 13 , further comprising:
 storing a plurality of entries in each of the at least one skid buffer, each entry for storing an instruction; and   indicating whether an associated instruction is valid in each of the at least one skid buffer.   
   
   
       16 . The method of  claim 13 , further comprising receiving a write signal at the at least one skid buffer each time an instruction is written into the at least one skid buffer. 
   
   
       17 . The method of  claim 13 , further comprising controlling a plurality of counters associated with the at least one skid buffer. 
   
   
       18 . The method of  claim 17 , wherein the controlling includes controlling a full count counter and generating a full signal to indicate that a skid buffer is full. 
   
   
       19 . The method of  claim 17 , wherein the controlling includes controlling an empty count counter and generating an empty signal to indicate that a skid buffer is empty. 
   
   
       20 . The method of  claim 17 , further comprising updating a valid bit of the at least one skid buffer. 
   
   
       21 . The method of  claim 17 , wherein the controlling includes controlling a commit pointer that specifies a next instruction to be committed and incrementing the commit pointer by a thread context (TC) committed signal. 
   
   
       22 . The method of  claim 17 , further comprising removing an instruction from the at least one skid buffer based on a signal from an execution pipeline. 
   
   
       23 . A computer-readable storage medium having computer program code embodied thereon that generates an apparatus in a multithreading processor configured to concurrently execute a plurality of threads of execution, the computer program code comprising:
 first computer-readable program code for providing at least one skid buffer coupled between an instruction fetch pipeline and an execution pipeline, and configured to store instructions of the plurality of threads after being dispatched to the execution pipeline,   wherein the at least one skid buffer is configured to re-issue instructions flushed from the execution pipeline to avoid re-fetching the flushed instructions from the instruction fetch pipeline.   
   
   
       24 . The computer-readable storage medium as recited in  claim 23 , wherein the at least one skid buffer is configured to receive a write signal each time an instruction is written into the at least one skid buffer. 
   
   
       25 . The computer-readable storage medium as recited in  claim 23 , further comprising second computer-readable program code for controlling a plurality of counters associated with the at least one skid buffer. 
   
   
       26 . The computer-readable storage medium as recited in  claim 25 , wherein the second program code further comprises third computer-readable program code for controlling a full count counter and generating a full signal to indicate that a skid buffer is full. 
   
   
       27 . The computer-readable storage medium as recited in  claim 25 , wherein the second computer-readable program code further comprises code for controlling an empty count counter and generating an empty signal to indicate that a skid buffer is empty. 
   
   
       28 . The computer-readable storage medium as recited in  claim 25 , wherein the second computer-readable program code further comprises code for updating a valid bit of the at least one skid buffer. 
   
   
       29 . The computer-readable storage medium as recited in  claim 25 , wherein the second computer-readable program code further comprises code for controlling a commit pointer that specifies a next instruction to be committed and incrementing the commit pointer by a thread context (TC) committed signal. 
   
   
       30 . The computer-readable storage medium as recited in  claim 25 , wherein the second computer-readable program code further comprises code for removing an instruction from the at least one skid buffer based on a signal from an execution pipeline.