Split gate type non-volatile memory device

Abstract

Embodiments relate to a gate structure of a split gate-type non-volatile memory device and a method of manufacturing the same. In embodiments, the split gate-type non-volatile memory device may include a device isolation layer formed on a semiconductor substrate in the direction of a bit line to define an active region, a pair of first conductive layer patterns formed on the active region, a charge storage layer interposed between the pair of first conductive layer patterns and the active region, a pair of second conductive layer pattern formed on the active region and extended along the one sidewalls of the pair of first conductive layer patterns in the direction parallel to a word line, and a gate insulating layer interposed between the pair of second conductive layer patterns and the active region. The pair of second conductive layer patterns may be formed on one sidewalls of the pair of first conductive layer patterns in the form of spacers.

1 - 20 . (canceled) 
   
   
       21 . A method, comprising:
 sequentially forming a charge storage layer, a first conductive layer and a capping insulating layer_having a prescribed width over a semiconductor substrate;   forming first insulating layers on outer sidewalls of the first conductive layer and gate insulating layers on the active region of the substrate;   forming a second conductive layer over the first conductive layer and the gate insulating layer;   forming second conductive layer patterns directly contacting the outer sidewall of the first insulating layers and the capping insulating layer_by performing a first etching process etching back the second conductive layer to thereby remove the second conductive layer from the entire uppermost surface of the capping insulating layer;   forming capping layer pattern and_a pair of first conductive layer patterns after forming the second conductive layer patterns by performing a second etching process etching the capping insulating layer and_a center portion of the first conductive layer to expose a portion of the uppermost surface of the semiconductor substrate and inner sidewalls of the first conductive layer; and then   forming second sidewall insulating layers on an inner sidewall of the first conductive layer patterns and an oxide layer on the exposed portion of the substrate.   
   
   
       22 . The method of  claim 21 , wherein the second conductive layer formed over the capping insulating layer and the semiconductor substrate is formed to be conformal. 
   
   
       23 . The method of  claim 21 , wherein the pair of second conductive layer patterns are formed on the right and left sidewalls of the first conductive layer and the capping insulating layer in the form of spacers such that the capping layer directly contacts the right and left sidewalls of the second conductive layer patterns. 
   
   
       24 . The method of  claim 21 , further comprising forming a photoresist pattern having an opening that crosses an active region on the first conductive layer to form the pair of first conductive layer patterns by etching 
   
   
       25 . The method of  claim 21 , wherein the gate insulating layers on the active region of the substrate is formed by performing a first thermal oxidation process;