Radio transmitter incorporating digital modulator and circuitry to accommodate baseband processor with analog interface

Abstract

A circuit provides a digital signal at optimal times to a digital processor of a transmitter. The circuit includes a complex analog-to-digital converter (ADC), a demodulator and a timing recovery circuit. The complex ADC is connected to receive an analog complex modulated baseband signal and to convert the analog complex modulated baseband signal to a digital complex modulated baseband signal. The demodulator operates to demodulate the digital signal to produce a demodulated digital signal for input to the digital processor. The timing recovery circuit receives a control signal and activates the digital processor based on a fixed timing relationship between receipt of the control signal at the timing recovery circuit and receipt of the analog complex modulated baseband signal at the complex ADC.

1 . A circuit connected to provide a digital signal to a digital processor of a transmitter, the circuit comprising:
 a complex analog-to-digital converter (ADC) connected to receive an analog complex modulated baseband signal, wherein the complex ADC is operable to convert the analog complex modulated baseband signal to a digital complex modulated baseband signal;   a demodulator connected to receive the digital complex modulated baseband signal, wherein the demodulator is operable to demodulate the digital signal to produce a demodulated digital signal for input to the digital processor; and   a timing recovery circuit connected to receive a control signal, wherein the timing recovery circuit is operable to activate the digital processor based on a fixed timing relationship between receipt of the control signal at the timing recovery circuit and receipt of the analog complex modulated baseband signal at the complex ADC.   
   
   
       2 . The circuit of  claim 1 , wherein the analog complex modulated baseband signal includes an in-phase signal and a quadrature phase signal, and wherein the complex ADC includes:
 a first analog-to-digital converter (ADC) connected to receive the in-phase signal, wherein the first ADC is operable to convert the in-phase signal to a first digital signal; and   a second ADC connected to receive the quadrature-phase signal, wherein the second ADC is operable to convert the quadrature-phase signal to a second digital signal.   
   
   
       3 . The circuit of  claim 2 , wherein at least one of the first analog-to-digital converter and the second analog-to-digital converters is a delta-sigma ADC. 
   
   
       4 . The circuit of  claim 2 , wherein the demodulator further includes:
 a first low pass filter connected to receive the first digital signal, wherein the first low pass filter is operable to filter the first digital signal to produce a first filtered digital signal; and   a second low pass filter connected to receive the second digital signal, wherein the second low pass filter is operable to filter the second digital signal to produce a second filtered digital signal.   
   
   
       5 . The circuit of  claim 4 , wherein at least one of the first low pass filter and the second low pass filter is a decimation filter operable to filter quantization noise and decrease a sample rate of  respective one of the first digital signal or the second digital signal. 
   
   
       6 . The circuit of  claim 4 , wherein the demodulator further includes:
 a vector de-rotator connected to receive the first filtered digital signal and the second filtered digital signal, wherein the vector de-rotator is operable to vector de-rotate the first filtered digital signal and the second filtered digital signal to produce a digitized baseband signal.   
   
   
       7 . The circuit of  claim 6 , wherein the vector de-rotator is a coordinate rotation digital computer (CORDIC) module. 
   
   
       8 . The circuit of  claim 6 , wherein the demodulator further includes:
 a phase locked loop connected to receive the digitized baseband signal, wherein the phase locked loop is operable to demodulate the digitized baseband signal to produce the demodulated digital signal;   a smoothing filter connected to receive the demodulated digital signal, wherein the smoothing filter is operable to apply a smoothing function to the demodulated digital signal to produce a smoothed digital signal; and   a slicer connected to receive the smoothed digital signal, wherein the slicer is operable to sample the smoothed digital signal to produce digital data.   
   
   
       9 . The circuit of  claim 8 , wherein an output of the timing recovery circuit enables the digital processor to read the digital data at optimal times corresponding to an output of the slicer. 
   
   
       10 . The circuit of  claim 9 , wherein the timing recovery circuit includes:
 a first counter programmable with a preset offset that defines the timing relationship; and   a second counter connected to count an output of the first counter, wherein the second counter is operable to produce a strobe signal having a periodic rate corresponding to the optimal times.   
   
   
       11 . A method for providing a digital signal to a digital processor of a transmitter, the method comprising:
 receiving an analog complex modulated baseband signal at a complex analog-to-digital converter (ADC);   converting the analog complex modulated baseband signal to a digital complex modulated baseband signal by the complex ADC;   demodulating the digital signal to produce a demodulated digital signal for input to the digital processor;   receiving a control signal at a timing recovery circuit; and   activating the digital processor based on a fixed timing relationship between receipt of the control signal at the timing recovery circuit and receipt of the analog complex modulated baseband signal at the complex ADC.   
   
   
       12 . The method of  claim 11 , wherein the analog complex modulated baseband signal includes an in-phase signal and a quadrature phase signal, and wherein the step of converting the analog complex modulated baseband signal to a digital complex modulated baseband signal further comprises:
 converting the in-phase signal to a first digital signal by a first analog-to-digital converter (ADC); and   converting the quadrature-phase signal to a second digital signal by a second ADC.   
   
   
       13 . The method of  claim 12 , wherein at least one of the first analog-to-digital converter and the second analog-to-digital converters is a delta-sigma ADC. 
   
   
       14 . The method of  claim 12 , wherein the step of demodulating further comprises:
 first filtering the first digital signal to produce a first filtered digital signal; and   second filtering the second digital signal to produce a second filtered digital signal.   
   
   
       15 . The method of  claim 14 , wherein at least one of the first filtering and the second filtering further comprises:
 filtering quantization noise; and   decreasing a sample rate of a respective one of the first digital signal or the second digital signal.   
   
   
       16 . The method of  claim 14 , wherein the step of demodulating further comprises:
 vector de-rotating the first filtered digital signal and the second filtered digital signal to produce a digitized baseband signal.   
   
   
       17 . The method of  claim 16 , wherein the step of vector de-rotating is performed by a coordinate rotation digital computer (CORDIC) module. 
   
   
       18 . The method of  claim 16 , wherein the step of demodulating further comprises:
 demodulating the digitized baseband signal by a phase locked loop to produce the demodulated digital signal;   applying a smoothing function by a smoothing filter to the demodulated digital signal to produce a smoothed digital signal; and   sampling the smoothed digital signal by a slicer to produce digital data.   
   
   
       19 . The method of  claim 18 , wherein the step of activating the digital processor further comprises:
 enabling, by an output of the timing recovery circuit, the digital processor to read the digital data at optimal times corresponding to an output of the slicer.   
   
   
       20 . The method of  claim 19 , wherein the step of activating the digital processor further comprises:
 programming a first counter of the timing recovery circuit with a preset offset that defines the timing relationship; and   producing, by a second counter connected to count an output of the first counter, a strobe signal having a periodic rate corresponding to the optimal times.